From patchwork Fri Oct 24 17:51:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 39491 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f69.google.com (mail-wg0-f69.google.com [74.125.82.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 15AF124026 for ; Fri, 24 Oct 2014 17:52:13 +0000 (UTC) Received: by mail-wg0-f69.google.com with SMTP id b13sf935794wgh.8 for ; Fri, 24 Oct 2014 10:52:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=kHfquThtNI//fZaN70GmNKWWWGnRze4BsShftyNFqkU=; b=KofFJCk4TXZLpVlZygvQV5/i1JM1djnWailViiG7wimEWWjImnqeASJraGZ0n1eG26 Fty7eVkAZA4f1j77oqYbsFjqa9GNp+bLxAhNqpRicZWXZq+3IRBhHq31WB6zSRO73XpP /xkGwbjuWaCk7XkF2K+J5gsjM/dGaCNP9+ccOTgw8+kHmGM1o5LvWvTzPdD05JIJ0cwU 77fFhn2imfnL57ymMKlD/I3KMR+zRvlM75lx31NtXzDaDbj/GlE6VENXmOLHTTpQBVLy YP6nAqRJKCFxaBqAHBMrWrofeJScR9Llh2gU7lJwAQfXz+uP+yIgwPc7ISitp59GHtGd 22zw== X-Gm-Message-State: ALoCoQnAJ5VUnqRhqFq3TR/aHuBuU3u/c4otkRladrsvOzIb/RZKqZmCv2YrAMraCqHNCwoWZYPZ X-Received: by 10.194.241.232 with SMTP id wl8mr730629wjc.5.1414173133285; Fri, 24 Oct 2014 10:52:13 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.115.231 with SMTP id jr7ls183479lab.104.gmail; Fri, 24 Oct 2014 10:52:13 -0700 (PDT) X-Received: by 10.112.198.226 with SMTP id jf2mr4921849lbc.84.1414173133088; Fri, 24 Oct 2014 10:52:13 -0700 (PDT) Received: from mail-lb0-f173.google.com (mail-lb0-f173.google.com. [209.85.217.173]) by mx.google.com with ESMTPS id d5si7989565laf.110.2014.10.24.10.52.12 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 24 Oct 2014 10:52:12 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by mail-lb0-f173.google.com with SMTP id 10so2983695lbg.32 for ; Fri, 24 Oct 2014 10:52:12 -0700 (PDT) X-Received: by 10.112.97.135 with SMTP id ea7mr6186154lbb.46.1414173132719; Fri, 24 Oct 2014 10:52:12 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.84.229 with SMTP id c5csp477077lbz; Fri, 24 Oct 2014 10:52:11 -0700 (PDT) X-Received: by 10.70.140.4 with SMTP id rc4mr6308816pdb.108.1414173131061; Fri, 24 Oct 2014 10:52:11 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ru12si4796938pac.48.2014.10.24.10.52.09 for ; Fri, 24 Oct 2014 10:52:11 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757033AbaJXRwG (ORCPT + 26 others); Fri, 24 Oct 2014 13:52:06 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:60094 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756791AbaJXRwA (ORCPT ); Fri, 24 Oct 2014 13:52:00 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9OHpaAQ006430; Fri, 24 Oct 2014 12:51:36 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9OHpaoa030543; Fri, 24 Oct 2014 12:51:36 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Fri, 24 Oct 2014 12:51:36 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9OHpYAI004463; Fri, 24 Oct 2014 12:51:36 -0500 From: Murali Karicheri To: , CC: Murali Karicheri Subject: [PATCH 4/4] ARM: keystone: dts: add DT bindings for PCI controller for port 1 Date: Fri, 24 Oct 2014 13:51:35 -0400 Message-ID: <1414173095-32511-5-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414173095-32511-1-git-send-email-m-karicheri2@ti.com> References: <1414173095-32511-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , K2E SoC has a second PCI port based on Synopsis Designware PCIe h/w. Add DT bindings to support PCI controller for port 1 for this SoC. Signed-off-by: Murali Karicheri CC : Santosh Shilimkar CC : Rob Herring CC : Pawel Moll CC : Mark Rutland CC : Ian Campbell CC : Kumar Gala CC : Russell King CC : devicetree@vger.kernel.org --- arch/arm/boot/dts/k2e.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi index c358b4b..e60d128 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/k2e.dtsi @@ -85,6 +85,51 @@ #gpio-cells = <2>; gpio,syscon-dev = <&devctrl 0x240>; }; + + pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 + 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, // INT A + <0 0 0 2 &pcie_intc1 1>, // INT B + <0 0 0 3 &pcie_intc1 2>, // INT C + <0 0 0 4 &pcie_intc1 3>; // INT D + + pcie_msi_intc1: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc1: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; }; };