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[82.45.1.190]) by mx.google.com with ESMTPSA id t7sm52235628wjy.24.2014.11.17.08.48.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Nov 2014 08:48:30 -0800 (PST) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, srinivas.kandagatla@gmail.com, patrice.chotard@st.com, arnd@arndb.de Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org Subject: [PATCH v3 06/11] ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks Date: Mon, 17 Nov 2014 16:47:59 +0000 Message-Id: <1416242884-5261-7-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1416242884-5261-1-git-send-email-peter.griffin@linaro.org> References: <1416242884-5261-1-git-send-email-peter.griffin@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.griffin@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Although most clock outputs are the same as stih407 SoC, stih410 also has some additional new clock outputs. Signed-off-by: Peter Griffin Acked-by: Lee Jones --- include/dt-bindings/clock/stih410-clks.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/clock/stih410-clks.h diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h new file mode 100644 index 0000000..2097a4b --- /dev/null +++ b/include/dt-bindings/clock/stih410-clks.h @@ -0,0 +1,25 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH410 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH410 +#define _DT_BINDINGS_CLK_STIH410 + +#include "stih407-clks.h" + +/* STiH410 introduces new clock outputs compared to STiH407 */ + +/* CLOCKGEN C0 */ +#define CLK_TX_ICN_HADES 32 +#define CLK_RX_ICN_HADES 33 +#define CLK_ICN_REG_16 34 +#define CLK_PP_HADES 35 +#define CLK_CLUST_HADES 36 +#define CLK_HWPE_HADES 37 +#define CLK_FC_HADES 38 + +/* CLOCKGEN D0 */ +#define CLK_PCMR10_MASTER 4 +#define CLK_USB2_PHY 5 + +#endif