From patchwork Tue Mar 17 10:11:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 45873 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f200.google.com (mail-lb0-f200.google.com [209.85.217.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9F67F2153C for ; Tue, 17 Mar 2015 10:14:04 +0000 (UTC) Received: by lbvn10 with SMTP id n10sf918951lbv.1 for ; Tue, 17 Mar 2015 03:14:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=zfG9QCCAcXaH1lDVFyuju2bE5AQLcXW495gwQ3Qq/Gs=; b=BbHBOw+d04pTbAfJBM28YdF4SD5Zhp/bEZbe5rkPW4x3Yb/Dpisv5shJDUhxkYlCEX tsxtJMJLCMNeWv6tDIqPnP9luy3ahR3292jSTKu+TnLCqDBkKl9tPRx68PLsSL0sgTkH 1UzNdupdwgCGETHHzoIx0Z29nUe8q9cCUOf2noxp1++h9bwMFmjLNMEd9rUKqLiqBgTw WiX75jQ4ocwDgz2mhCC/6e2IUwOrUtYiaCAUT8/oaDIqADbkLsf04VB24fNHJkS0Pa/m Nj9Vt5UiMFAVhCvxhwZ0r1HfQFfFe5DScU9t+kpUJ7OvFWPn3QRRU+fka7lQJj+jclpN IvIQ== X-Gm-Message-State: ALoCoQlxIyTVi8cSGoiLzHEg1X7nO7duZoU7jRHGlNThKVLmJ+0HGv+mOKwQMdJIrxlLlcN7c8OG X-Received: by 10.152.164.171 with SMTP id yr11mr6992594lab.4.1426587243180; Tue, 17 Mar 2015 03:14:03 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.22.65 with SMTP id b1ls16581laf.99.gmail; Tue, 17 Mar 2015 03:14:02 -0700 (PDT) X-Received: by 10.152.29.166 with SMTP id l6mr60351359lah.78.1426587242703; Tue, 17 Mar 2015 03:14:02 -0700 (PDT) Received: from mail-lb0-f182.google.com (mail-lb0-f182.google.com. [209.85.217.182]) by mx.google.com with ESMTPS id xs4si10175411lab.5.2015.03.17.03.14.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Mar 2015 03:14:02 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.182 as permitted sender) client-ip=209.85.217.182; Received: by lbcgn8 with SMTP id gn8so3388092lbc.2 for ; Tue, 17 Mar 2015 03:14:02 -0700 (PDT) X-Received: by 10.152.29.68 with SMTP id i4mr9518377lah.19.1426587242593; Tue, 17 Mar 2015 03:14:02 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.35.133 with SMTP id h5csp403068lbj; Tue, 17 Mar 2015 03:14:01 -0700 (PDT) X-Received: by 10.66.66.108 with SMTP id e12mr150077200pat.31.1426587240517; Tue, 17 Mar 2015 03:14:00 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id m1si28398055pdb.45.2015.03.17.03.13.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Mar 2015 03:14:00 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YXoUK-0003Ty-0w; Tue, 17 Mar 2015 10:12:40 +0000 Received: from mail-wg0-f53.google.com ([74.125.82.53]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YXoTY-00038M-Ta for linux-arm-kernel@lists.infradead.org; Tue, 17 Mar 2015 10:11:54 +0000 Received: by wgdm6 with SMTP id m6so4179350wgd.2 for ; Tue, 17 Mar 2015 03:11:30 -0700 (PDT) X-Received: by 10.194.63.16 with SMTP id c16mr133227796wjs.117.1426587090002; Tue, 17 Mar 2015 03:11:30 -0700 (PDT) Received: from ards-macbook-pro.local ([90.174.4.220]) by mx.google.com with ESMTPSA id r3sm19260430wjw.7.2015.03.17.03.11.28 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 17 Mar 2015 03:11:29 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, marc.zyngier@arm.com Subject: [PATCH 2/3] arm64: remove __calc_phys_offset Date: Tue, 17 Mar 2015 11:11:13 +0100 Message-Id: <1426587074-22390-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1426587074-22390-1-git-send-email-ard.biesheuvel@linaro.org> References: <1426587074-22390-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150317_031153_163775_3EAC30C3 X-CRM114-Status: UNSURE ( 9.68 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.53 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.53 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This removes the function __calc_phys_offset and all open coded virtual to physical address translations using the offset kept in x28. Instead, just use absolute or PC-relative symbol references as appropriate when referring to virtual or physical addresses, respectively. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 49 ++++++++++++------------------------------------ 1 file changed, 12 insertions(+), 37 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index fb912314d5e1..1651c0fd50e6 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -36,8 +36,6 @@ #include #include -#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) - #if (TEXT_OFFSET & 0xfff) != 0 #error TEXT_OFFSET must be at least 4KB aligned #elif (PAGE_OFFSET & 0x1fffff) != 0 @@ -46,13 +44,6 @@ #error TEXT_OFFSET must be less than 2MB #endif - .macro pgtbl, ttb0, ttb1, virt_to_phys - ldr \ttb1, =swapper_pg_dir - ldr \ttb0, =idmap_pg_dir - add \ttb1, \ttb1, \virt_to_phys - add \ttb0, \ttb0, \virt_to_phys - .endm - #ifdef CONFIG_ARM64_64K_PAGES #define BLOCK_SHIFT PAGE_SHIFT #define BLOCK_SIZE PAGE_SIZE @@ -63,7 +54,7 @@ #define TABLE_SHIFT PUD_SHIFT #endif -#define KERNEL_START KERNEL_RAM_VADDR +#define KERNEL_START _text #define KERNEL_END _end /* @@ -242,7 +233,7 @@ section_table: ENTRY(stext) mov x21, x0 // x21=FDT bl el2_setup // Drop to EL1, w20=cpu_boot_mode - bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET + adrp x24, KERNEL_START - TEXT_OFFSET // x24=PHYS_OFFSET bl set_cpu_boot_mode_flag bl __vet_fdt @@ -343,7 +334,8 @@ ENDPROC(__vet_fdt) * - pgd entry for fixed mappings (TTBR1) */ __create_page_tables: - pgtbl x25, x26, x28 // idmap_pg_dir and swapper_pg_dir addresses + adrp x25, idmap_pg_dir + adrp x26, swapper_pg_dir mov x27, lr /* @@ -372,12 +364,10 @@ __create_page_tables: * Create the identity mapping. */ mov x0, x25 // idmap_pg_dir - ldr x3, =KERNEL_START - add x3, x3, x28 // __pa(KERNEL_START) + adrp x3, KERNEL_START // __pa(KERNEL_START) create_pgd_entry x0, x3, x5, x6 - ldr x6, =KERNEL_END mov x5, x3 // __pa(KERNEL_START) - add x6, x6, x28 // __pa(KERNEL_END) + adr_l x6, KERNEL_END // __pa(KERNEL_END) create_block_map x0, x7, x3, x5, x6 /* @@ -386,7 +376,7 @@ __create_page_tables: mov x0, x26 // swapper_pg_dir mov x5, #PAGE_OFFSET create_pgd_entry x0, x5, x3, x6 - ldr x6, =KERNEL_END + ldr x6, =KERNEL_END // __va(KERNEL_END) mov x3, x24 // phys offset create_block_map x0, x7, x3, x5, x6 @@ -538,8 +528,7 @@ ENDPROC(el2_setup) * in x20. See arch/arm64/include/asm/virt.h for more info. */ ENTRY(set_cpu_boot_mode_flag) - ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode - add x1, x1, x28 + adr_l x1, __boot_cpu_mode cmp w20, #BOOT_CPU_MODE_EL2 b.ne 1f add x1, x1, #4 @@ -570,7 +559,7 @@ ENTRY(__boot_cpu_mode) */ ENTRY(secondary_holding_pen) bl el2_setup // Drop to EL1, w20=cpu_boot_mode - bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET + adrp x24, KERNEL_START - TEXT_OFFSET // x24=PHYS_OFFSET bl set_cpu_boot_mode_flag mrs x0, mpidr_el1 ldr x1, =MPIDR_HWID_BITMASK @@ -589,7 +578,7 @@ ENDPROC(secondary_holding_pen) */ ENTRY(secondary_entry) bl el2_setup // Drop to EL1 - bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET + adrp x24, KERNEL_START - TEXT_OFFSET // x24=PHYS_OFFSET bl set_cpu_boot_mode_flag b secondary_startup ENDPROC(secondary_entry) @@ -598,7 +587,8 @@ ENTRY(secondary_startup) /* * Common entry point for secondary CPUs. */ - pgtbl x25, x26, x28 // x25=TTBR0, x26=TTBR1 + adrp x25, idmap_pg_dir + adrp x26, swapper_pg_dir bl __cpu_setup // initialise processor ldr x21, =secondary_data @@ -636,18 +626,3 @@ __enable_mmu: isb br x27 ENDPROC(__enable_mmu) - -/* - * Calculate the start of physical memory. - */ -__calc_phys_offset: - adr x0, 1f - ldp x1, x2, [x0] - sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET - add x24, x2, x28 // x24 = PHYS_OFFSET - ret -ENDPROC(__calc_phys_offset) - - .align 3 -1: .quad . - .quad PAGE_OFFSET