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[91.152.81.141]) by mx.google.com with ESMTPSA id ds8sm258425lbb.18.2015.04.10.00.16.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Apr 2015 00:16:45 -0700 (PDT) From: Fathi Boudra To: linux-arm-kernel@lists.infradead.org, Olof Johansson , Arnd Bergmann Subject: [PATCH 1/2] ARM: dts: add HiSilicon hip04 ethernet controller resource Date: Fri, 10 Apr 2015 10:16:19 +0300 Message-Id: <1428650180-9746-2-git-send-email-fathi.boudra@linaro.org> X-Mailer: git-send-email 2.3.5 In-Reply-To: <1428650180-9746-1-git-send-email-fathi.boudra@linaro.org> References: <1428650180-9746-1-git-send-email-fathi.boudra@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150410_001709_408243_81986369 X-CRM114-Status: UNSURE ( 8.77 ) X-CRM114-Notice: Please train this message. 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X-Original-Sender: fathi.boudra@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 add the device tree binding for the HiSilicon hip04 ethernet controller based on Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt Signed-off-by: Zhangfei Gao Signed-off-by: Fathi Boudra --- arch/arm/boot/dts/hip04.dtsi | 49 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 2388145..fc68753 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -269,6 +269,55 @@ interrupts = <0 372 4>; }; + mdio { + compatible = "hisilicon,hip04-mdio"; + reg = <0x28f1000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + }; + + ppe: ppe@28c0000 { + compatible = "hisilicon,hip04-ppe", "syscon"; + reg = <0x28c0000 0x10000>; + }; + + fe: ethernet@28b0000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x28b0000 0x10000>; + interrupts = <0 413 4>; + phy-mode = "mii"; + port-handle = <&ppe 31 0>; + }; + + ge0: ethernet@2800000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2800000 0x10000>; + interrupts = <0 402 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 0 1>; + phy-handle = <&phy0>; + }; + + ge8: ethernet@2880000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2880000 0x10000>; + interrupts = <0 410 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 8 2>; + phy-handle = <&phy1>; + }; }; etb@0,e3c42000 {