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[2001:1868:205::9]) by mx.google.com with ESMTPS id w16si26318057pbt.152.2015.07.05.19.19.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Jul 2015 19:19:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBvzR-0005ub-AS; Mon, 06 Jul 2015 02:18:37 +0000 Received: from mail-pa0-f48.google.com ([209.85.220.48]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBvzK-0005nN-6R for linux-arm-kernel@lists.infradead.org; Mon, 06 Jul 2015 02:18:31 +0000 Received: by pacgz10 with SMTP id gz10so13146947pac.3 for ; Sun, 05 Jul 2015 19:18:09 -0700 (PDT) X-Received: by 10.70.137.39 with SMTP id qf7mr43098870pdb.39.1436149089061; Sun, 05 Jul 2015 19:18:09 -0700 (PDT) Received: from localhost ([120.136.34.248]) by mx.google.com with ESMTPSA id wa4sm16261278pab.17.2015.07.05.19.18.07 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 05 Jul 2015 19:18:08 -0700 (PDT) From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Subject: [PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers Date: Mon, 6 Jul 2015 10:17:33 +0800 Message-Id: <1436149068-3784-4-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> References: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150705_191830_267234_9D61A38A X-CRM114-Status: GOOD ( 11.07 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.48 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.48 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59 +++++++++++++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 3c5fe68..21b5d3b 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -56,14 +56,36 @@ #define DBGWVR15_EL1 86 #define MDCCINT_EL1 87 /* Monitor Debug Comms Channel Interrupt Enable Reg */ +/* Performance Monitors Registers */ +#define PMCR_EL0 88 /* Control Register */ +#define PMOVSSET_EL0 89 /* Overflow Flag Status Set Register */ +#define PMOVSCLR_EL0 90 /* Overflow Flag Status Clear Register */ +#define PMCCNTR_EL0 91 /* Cycle Counter Register */ +#define PMSELR_EL0 92 /* Event Counter Selection Register */ +#define PMCEID0_EL0 93 /* Common Event Identification Register 0 */ +#define PMCEID1_EL0 94 /* Common Event Identification Register 1 */ +#define PMEVCNTR0_EL0 95 /* Event Counter Register (0-30) */ +#define PMEVTYPER0_EL0 96 /* Event Type Register (0-30) */ +#define PMEVCNTR30_EL0 155 +#define PMEVTYPER30_EL0 156 +#define PMXEVCNTR_EL0 157 /* Selected Event Count Register */ +#define PMXEVTYPER_EL0 158 /* Selected Event Type Register */ +#define PMCNTENSET_EL0 159 /* Count Enable Set Register */ +#define PMCNTENCLR_EL0 160 /* Count Enable Clear Register */ +#define PMINTENSET_EL1 161 /* Interrupt Enable Set Register */ +#define PMINTENCLR_EL1 162 /* Interrupt Enable Clear Register */ +#define PMUSERENR_EL0 163 /* User Enable Register */ +#define PMCCFILTR_EL0 164 /* Cycle Count Filter Register */ +#define PMSWINC_EL0 165 /* Software Increment Register */ + /* 32bit specific registers. Keep them at the end of the range */ -#define DACR32_EL2 88 /* Domain Access Control Register */ -#define IFSR32_EL2 89 /* Instruction Fault Status Register */ -#define FPEXC32_EL2 90 /* Floating-Point Exception Control Register */ -#define DBGVCR32_EL2 91 /* Debug Vector Catch Register */ -#define TEECR32_EL1 92 /* ThumbEE Configuration Register */ -#define TEEHBR32_EL1 93 /* ThumbEE Handler Base Register */ -#define NR_SYS_REGS 94 +#define DACR32_EL2 166 /* Domain Access Control Register */ +#define IFSR32_EL2 167 /* Instruction Fault Status Register */ +#define FPEXC32_EL2 168 /* Floating-Point Exception Control Register */ +#define DBGVCR32_EL2 169 /* Debug Vector Catch Register */ +#define TEECR32_EL1 170 /* ThumbEE Configuration Register */ +#define TEEHBR32_EL1 171 /* ThumbEE Handler Base Register */ +#define NR_SYS_REGS 172 /* 32bit mapping */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ @@ -85,6 +107,24 @@ #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ + +/* Performance Monitors*/ +#define c9_PMCR (PMCR_EL0 * 2) +#define c9_PMOVSSET (PMOVSSET_EL0 * 2) +#define c9_PMOVSCLR (PMOVSCLR_EL0 * 2) +#define c9_PMCCNTR (PMCCNTR_EL0 * 2) +#define c9_PMSELR (PMSELR_EL0 * 2) +#define c9_PMCEID0 (PMCEID0_EL0 * 2) +#define c9_PMCEID1 (PMCEID1_EL0 * 2) +#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2) +#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2) +#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2) +#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2) +#define c9_PMINTENSET (PMINTENSET_EL1 * 2) +#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2) +#define c9_PMUSERENR (PMUSERENR_EL0 * 2) +#define c9_PMSWINC (PMSWINC_EL0 * 2) + #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ @@ -96,6 +136,11 @@ #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ +/* Performance Monitors*/ +#define c14_PMEVCNTR0 (PMEVCNTR0_EL0 * 2) +#define c14_PMEVTYPR0 (PMEVTYPER0_EL0 * 2) +#define c14_PMCCFILTR (PMCCFILTR_EL0 * 2) + #define cp14_DBGDSCRext (MDSCR_EL1 * 2) #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)