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[209.132.180.67]) by mx.google.com with ESMTP id f4si5936223pas.118.2015.07.15.00.07.44; Wed, 15 Jul 2015 00:07:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751598AbbGOHHn (ORCPT + 8 others); Wed, 15 Jul 2015 03:07:43 -0400 Received: from mail-pa0-f52.google.com ([209.85.220.52]:33934 "EHLO mail-pa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750946AbbGOHHn (ORCPT ); Wed, 15 Jul 2015 03:07:43 -0400 Received: by pacan13 with SMTP id an13so19242921pac.1 for ; Wed, 15 Jul 2015 00:07:42 -0700 (PDT) X-Received: by 10.66.121.163 with SMTP id ll3mr5287703pab.100.1436944062718; Wed, 15 Jul 2015 00:07:42 -0700 (PDT) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id cz1sm3457924pbc.84.2015.07.15.00.07.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Jul 2015 00:07:41 -0700 (PDT) From: Chunyan Zhang To: arm@kernel.org Cc: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, zhang.lyra@gmail.com Subject: [PATCH] arm64: dts: sprd: adding ETM entries to Spreadtrum SC9836 Date: Wed, 15 Jul 2015 15:05:48 +0800 Message-Id: <1436943948-14489-1-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhang.chunyan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Since ETMv4 driver has been merged, this patch adds ETM nodes for SC9836, and four funnel input ports to connect with ETM output ports. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9836.dtsi | 99 ++++++++++++++++++++++++++++++++++-- 1 file changed, 94 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index ee34e1a..63894c4 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -16,28 +16,28 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; @@ -75,14 +75,103 @@ }; }; - /* funnel input port 0~3 is reserved for ETMs */ + /* funnel input port 0-4 */ port@1 { + reg = <0>; + funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out>; + }; + }; + + port@2 { + reg = <1>; + funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out>; + }; + }; + + port@3 { + reg = <2>; + funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&etm2_out>; + }; + }; + + port@4 { + reg = <3>; + funnel_in_port3: endpoint { + slave-mode; + remote-endpoint = <&etm3_out>; + }; + }; + + port@5 { reg = <4>; funnel_in_port4: endpoint { slave-mode; remote-endpoint = <&stm_out>; }; }; + /* Other input ports aren't connected to anyone */ + }; + }; + + etm@10440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x10440000 0 0x1000>; + + cpu = <&cpu0>; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + + etm@10540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x10540000 0 0x1000>; + + cpu = <&cpu1>; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + + etm@10640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x10640000 0 0x1000>; + + cpu = <&cpu2>; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; + }; + }; + + etm@10740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x10740000 0 0x1000>; + + cpu = <&cpu3>; + clocks = <&clk26mhz>; + clock-names = "apb_pclk"; + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_in_port3>; + }; }; };