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[2001:1868:205::9]) by mx.google.com with ESMTPS id ga17si3317589wic.55.2015.09.09.01.41.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Sep 2015 01:41:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZZauk-0007P8-71; Wed, 09 Sep 2015 08:39:34 +0000 Received: from mail-pa0-f52.google.com ([209.85.220.52]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZZauf-0007IZ-Hz for linux-arm-kernel@lists.infradead.org; Wed, 09 Sep 2015 08:39:30 +0000 Received: by padhk3 with SMTP id hk3so3776191pad.3 for ; Wed, 09 Sep 2015 01:39:09 -0700 (PDT) X-Received: by 10.66.235.4 with SMTP id ui4mr37595217pac.119.1441787948881; Wed, 09 Sep 2015 01:39:08 -0700 (PDT) Received: from pnqlab044.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id uy4sm6110798pbc.69.2015.09.09.01.39.04 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Sep 2015 01:39:07 -0700 (PDT) From: Tushar Jagad To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Subject: [PATCH RFC 1/4] arm64: KVM: add MIDR_EL1 switching Date: Wed, 9 Sep 2015 14:08:31 +0530 Message-Id: <1441787914-3191-2-git-send-email-tushar.jagad@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441787914-3191-1-git-send-email-tushar.jagad@linaro.org> References: <1441787914-3191-1-git-send-email-tushar.jagad@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150909_013929_628450_ACE2DA4A X-CRM114-Status: GOOD ( 18.02 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.52 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.52 listed in wl.mailspike.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, patches@apm.com, qemu-devel@nongnu.org, tushar.jagad@linaro.org, christoffer.dall@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: tushar.jagad@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Marc Zyngier Move MIDR_EL1 to be a world-switched register, instead of being unchanged from the host. The behaviour is preserved by using the host's MIDR_EL1 as a reset value for the guest's register. Signed-off-by: Marc Zyngier Signed-off-by: Tushar Jagad --- arch/arm64/include/asm/kvm_asm.h | 16 +++++++++------- arch/arm64/kvm/hyp.S | 4 ++++ arch/arm64/kvm/sys_regs.c | 18 +++++++++++++----- 3 files changed, 26 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 3c5fe68..c1d5bde 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -55,17 +55,19 @@ #define DBGWVR0_EL1 71 /* Debug Watchpoint Value Registers (0-15) */ #define DBGWVR15_EL1 86 #define MDCCINT_EL1 87 /* Monitor Debug Comms Channel Interrupt Enable Reg */ +#define MIDR_EL1 88 /* Main ID Register */ /* 32bit specific registers. Keep them at the end of the range */ -#define DACR32_EL2 88 /* Domain Access Control Register */ -#define IFSR32_EL2 89 /* Instruction Fault Status Register */ -#define FPEXC32_EL2 90 /* Floating-Point Exception Control Register */ -#define DBGVCR32_EL2 91 /* Debug Vector Catch Register */ -#define TEECR32_EL1 92 /* ThumbEE Configuration Register */ -#define TEEHBR32_EL1 93 /* ThumbEE Handler Base Register */ -#define NR_SYS_REGS 94 +#define DACR32_EL2 89 /* Domain Access Control Register */ +#define IFSR32_EL2 90 /* Instruction Fault Status Register */ +#define FPEXC32_EL2 91 /* Floating-Point Exception Control Register */ +#define DBGVCR32_EL2 92 /* Debug Vector Catch Register */ +#define TEECR32_EL1 93 /* ThumbEE Configuration Register */ +#define TEEHBR32_EL1 94 /* ThumbEE Handler Base Register */ +#define NR_SYS_REGS 95 /* 32bit mapping */ +#define c0_MIDR (MIDR_EL1 * 2) /* Main ID Register */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 17a8fb1..6013347 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -216,6 +216,7 @@ mrs x23, cntkctl_el1 mrs x24, par_el1 mrs x25, mdscr_el1 + mrs x26, vpidr_el2 stp x4, x5, [x3] stp x6, x7, [x3, #16] @@ -228,6 +229,7 @@ stp x20, x21, [x3, #128] stp x22, x23, [x3, #144] stp x24, x25, [x3, #160] + str x26, [x3, #696] .endm .macro save_debug @@ -442,6 +444,7 @@ ldp x20, x21, [x3, #128] ldp x22, x23, [x3, #144] ldp x24, x25, [x3, #160] + ldr x26, [x3, #696] msr vmpidr_el2, x4 msr csselr_el1, x5 @@ -465,6 +468,7 @@ msr cntkctl_el1, x23 msr par_el1, x24 msr mdscr_el1, x25 + msr vpidr_el2, x26 .endm .macro restore_debug diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c370b40..7047292 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -170,17 +170,25 @@ static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, } } +static void reset_midr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + /* + * We only export the host's MPIDR_EL1 for now. + */ + vcpu_sys_reg(vcpu, MIDR_EL1) = read_cpuid_id(); +} + /* * We want to avoid world-switching all the DBG registers all the * time: - * + * * - If we've touched any debug register, it is likely that we're * going to touch more of them. It then makes sense to disable the * traps and start doing the save/restore dance * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is * then mandatory to save/restore the registers, as the guest * depends on them. - * + * * For this, we use a DIRTY bit, indicating the guest has modified the * debug registers, used as follow: * @@ -350,6 +358,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000), NULL, reset_val, DBGVCR32_EL2, 0 }, + /* MIDR_EL1 */ + { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000), + NULL, reset_midr, MIDR_EL1 }, /* MPIDR_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101), NULL, reset_mpidr, MPIDR_EL1 }, @@ -1091,7 +1102,6 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, ((struct sys_reg_desc *)r)->val = val; \ } -FUNCTION_INVARIANT(midr_el1) FUNCTION_INVARIANT(ctr_el0) FUNCTION_INVARIANT(revidr_el1) FUNCTION_INVARIANT(id_pfr0_el1) @@ -1113,8 +1123,6 @@ FUNCTION_INVARIANT(aidr_el1) /* ->val is filled in by kvm_sys_reg_table_init() */ static struct sys_reg_desc invariant_sys_regs[] = { - { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000), - NULL, get_midr_el1 }, { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110), NULL, get_revidr_el1 }, { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),