From patchwork Fri Sep 11 08:55:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 53415 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f200.google.com (mail-lb0-f200.google.com [209.85.217.200]) by patches.linaro.org (Postfix) with ESMTPS id 6C3B122B26 for ; Fri, 11 Sep 2015 08:59:30 +0000 (UTC) Received: by lbbti1 with SMTP id ti1sf22186399lbb.3 for ; Fri, 11 Sep 2015 01:59:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:mime-version:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe:cc :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=38AAcfR0FB088gKGp+/SGsQxWxLd3TdXiHRLQk0ciW8=; b=cO5Ftv3yTrj5zQBUOG23v/CmvhvFWAYIiLIewGGv+EKG9TgBwfGYDbtNMD5gjxOPgh wzW80yiWcfEtd5RdNJvU0qquu59D4GIQzRLp5lE7Ou1vicJrr9UucJvP1svXxT3Er6CA G/8Ku3ueHQwCepr9PsPcYQ6BLIpo8s3sQJ9aY7I0i02yX8MSMaxg1NI89HVPLOH6McYj q/Dpp8Vr9XmDtOeGmc27AROd8j01cB8nGENDqVyoe3NQ83ulP2xO5u36+Xf1BDhDNT8z 0K7LjTiC/HsHZwZYECQL/ivq6bLM/1VO34AdAhbIyb4+oE/ztJb/dh5qh+VwbkWNEDj9 BSdA== X-Gm-Message-State: ALoCoQl1JmKyb+Fc3dV2Mca+U63lATrNXS9lQVBKXr+bYL//jUM0zowjG0NM7/laLfZ7cbtrz0Bc X-Received: by 10.112.16.200 with SMTP id i8mr11043944lbd.20.1441961969421; Fri, 11 Sep 2015 01:59:29 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.19.231 with SMTP id i7ls303706lae.1.gmail; Fri, 11 Sep 2015 01:59:29 -0700 (PDT) X-Received: by 10.112.198.198 with SMTP id je6mr24677217lbc.31.1441961969290; Fri, 11 Sep 2015 01:59:29 -0700 (PDT) Received: from mail-la0-f43.google.com (mail-la0-f43.google.com. [209.85.215.43]) by mx.google.com with ESMTPS id n7si361488lbd.127.2015.09.11.01.59.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2015 01:59:29 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) client-ip=209.85.215.43; Received: by lahg1 with SMTP id g1so13626251lah.1 for ; Fri, 11 Sep 2015 01:59:29 -0700 (PDT) X-Received: by 10.152.178.165 with SMTP id cz5mr40416019lac.29.1441961969173; Fri, 11 Sep 2015 01:59:29 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1447841lbq; Fri, 11 Sep 2015 01:59:28 -0700 (PDT) X-Received: by 10.67.5.228 with SMTP id cp4mr86091012pad.120.1441961968000; Fri, 11 Sep 2015 01:59:28 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id ho2si996814pad.29.2015.09.11.01.59.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2015 01:59:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK9w-0001zx-N6; Fri, 11 Sep 2015 08:58:16 +0000 Received: from merlin.infradead.org ([205.233.59.134]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK90-00013O-EX for linux-arm-kernel@bombadil.infradead.org; Fri, 11 Sep 2015 08:57:18 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZaK8s-0001YT-At for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2015 08:57:13 +0000 Received: from 172.24.1.48 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.48]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CUU27190; Fri, 11 Sep 2015 16:56:04 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Fri, 11 Sep 2015 16:55:52 +0800 From: Shannon Zhao To: Subject: [PATCH v2 17/22] KVM: ARM64: Add reset and access handlers for PMSWINC register Date: Fri, 11 Sep 2015 16:55:10 +0800 Message-ID: <1441961715-11688-18-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> References: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150911_045711_927125_24006580 X-CRM114-Status: GOOD ( 16.19 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +++++++++++++++++- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b47cd0b..24d00a0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -335,6 +335,11 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~val; break; } + case PMSWINC_EL0: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_software_increment(vcpu, val); + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -364,6 +369,8 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, *vcpu_reg(vcpu, p->Rt) = val; break; } + case PMSWINC_EL0: + return read_zero(vcpu, p); default: *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); break; @@ -576,7 +583,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMOVSCLR_EL0 }, /* PMSWINC_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMSWINC_EL0 }, /* PMSELR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), access_pmu_regs, reset_unknown, PMSELR_EL0 }, @@ -833,6 +840,11 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, c9_PMOVSSET) &= ~val; break; } + case c9_PMSWINC: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_software_increment(vcpu, val); + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -862,6 +874,8 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, *vcpu_reg(vcpu, p->Rt) = val; break; } + case c9_PMSWINC: + return read_zero(vcpu, p); default: *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg); break; @@ -907,6 +921,8 @@ static const struct sys_reg_desc cp15_regs[] = { reset_unknown_cp15, c9_PMCNTENCLR }, { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMOVSCLR }, + { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMSWINC }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMSELR }, { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 59e70af..1a27357 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -41,6 +41,7 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, unsigned long select_idx); void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val); +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, unsigned long val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx); #else @@ -51,6 +52,7 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, } void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) {} +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, unsigned long val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, unsigned long select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index c6cdc4e..5f5a483 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -163,6 +163,35 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) } /** + * kvm_pmu_software_increment - do software increment + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMSWINC register + */ +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, unsigned long val) +{ + int i; + unsigned int type, enable; + + for (i = 0; i < 32; i++) { + if ((val >> i) & 0x1) { + if (!vcpu_mode_is_32bit(vcpu)) { + type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i) + & ARMV8_EVTYPE_EVENT; + enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0); + if ((type == 0) && ((enable >> i) & 0x1)) + vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i)++; + } else { + type = vcpu_cp15(vcpu, c14_PMEVTYPER0 + i) + & ARMV8_EVTYPE_EVENT; + enable = vcpu_cp15(vcpu, c9_PMCNTENSET); + if ((type == 0) && ((enable >> i) & 0x1)) + vcpu_cp15(vcpu, c14_PMEVCNTR0 + i)++; + } + } + } +} + +/** * kvm_pmu_find_hw_event - find hardware event * @pmu: The pmu pointer * @event_select: The number of selected event type @@ -239,6 +268,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data, kvm_pmu_stop_counter(vcpu, select_idx); kvm_pmu_set_evttyper(vcpu, select_idx, data); + /* For software increment event we don't need to create perf event */ + if (new_eventsel == 0) + return; + config = kvm_pmu_find_hw_event(pmu, new_eventsel); if (config != PERF_COUNT_HW_MAX) { type = PERF_TYPE_HARDWARE;