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[209.132.180.67]) by mx.google.com with ESMTP id ek3si33236332pbb.43.2015.09.15.09.52.36; Tue, 15 Sep 2015 09:52:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753538AbbIOQwZ (ORCPT + 29 others); Tue, 15 Sep 2015 12:52:25 -0400 Received: from fw-tnat.cambridge.arm.com ([217.140.96.140]:55736 "EHLO cam-smtp0.cambridge.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753494AbbIOQwU (ORCPT ); Tue, 15 Sep 2015 12:52:20 -0400 Received: from e105922-lin.cambridge.arm.com (e105922-lin.cambridge.arm.com [10.2.135.144]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with SMTP id t8FGpmRF002570; Tue, 15 Sep 2015 17:51:48 +0100 Received: by e105922-lin.cambridge.arm.com (sSMTP sendmail emulation); Tue, 15 Sep 2015 17:51:48 +0100 From: Punit Agrawal To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, edubezval@gmail.com, sudeep.holla@arm.com, liviu.dudau@arm.com, linux@roeck-us.net, Punit Agrawal Subject: [PATCH v4 1/5] Documentation: add DT bindings for ARM SCPI sensors Date: Tue, 15 Sep 2015 17:50:57 +0100 Message-Id: <1442335861-7282-2-git-send-email-punit.agrawal@arm.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1442335861-7282-1-git-send-email-punit.agrawal@arm.com> References: <1442335861-7282-1-git-send-email-punit.agrawal@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: punit.agrawal@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The System Control Processor (SCP) provides access to SoC sensors via the System Control and Power Interface (SCPI) Message Protocol. Add bindings to allow probing of these sensors. Also support referencing of the sensors for setting up thermal zones via the thermal DT bindings. Signed-off-by: Punit Agrawal Cc: Rob Herring Cc: Mark Rutland Cc: Sudeep Holla Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/arm,scpi.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index f002460..86302de 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -72,8 +72,25 @@ Required sub-node properties: - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based shared memory on Juno platforms +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "arm,scpi-sensors". +- #thermal-sensor-cells: should be set to 1. This property follows the + thermal device tree bindings[2]. + + Valid cell values are raw identifiers (Sensor + ID) as used by the firmware. Refer to + platform documentation for your + implementation for the IDs to use. For Juno + R0 and Juno R1 refer to [3]. + [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/thermal/thermal.txt +[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html Example: @@ -122,6 +139,11 @@ scpi_protocol: scpi@2e000000 { clock-output-names = "pxlclk0", "pxlclk1"; }; }; + + scpi_sensors0: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; }; cpu@0 { @@ -136,6 +158,17 @@ hdlcd@7ff60000 { clocks = <&scpi_clk 4>; }; +thermal-zones { + soc_thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + /* sensor ID */ + thermal-sensors = <&scpi_sensors0 3>; + ... + }; +}; + In the above example, the #clock-cells is set to 1 as required. scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0, 1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 @@ -148,3 +181,8 @@ scpi_dvfs i.e. "atlclk". Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input clock. '4' in the clock specifier here points to the second entry in the output clocks of scpi_clocks i.e. "pxlclk1" + +The thermal-sensors property in the soc_thermal node uses the +temperature sensor provided by SCP firmware to setup a thermal +zone. The ID "3" is the sensor identifier for the temperature sensor +as used by the firmware.