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[209.132.180.67]) by mx.google.com with ESMTP id j199si7539426ioe.58.2015.09.18.09.31.42; Fri, 18 Sep 2015 09:31:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932129AbbIRQbl (ORCPT + 30 others); Fri, 18 Sep 2015 12:31:41 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:34772 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932069AbbIRQ1O (ORCPT ); Fri, 18 Sep 2015 12:27:14 -0400 Received: by padhy16 with SMTP id hy16so55269642pad.1 for ; Fri, 18 Sep 2015 09:27:13 -0700 (PDT) X-Received: by 10.66.144.165 with SMTP id sn5mr8394725pab.122.1442593633221; Fri, 18 Sep 2015 09:27:13 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.11 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:12 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 08/20] coresight: etb10: implementing buffer set and unset APIs Date: Fri, 18 Sep 2015 10:26:22 -0600 Message-Id: <1442593594-10665-9-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implementing perf related APIs to activate and terminate a trace session. More specifically dealing with the sink buffer's internal mechanic along with perf's API to start and stop interactions with the ring buffers. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 42 +++++++++++++++++++++++++++ include/linux/coresight.h | 8 +++++ 2 files changed, 50 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index ca2fbf65a454..3239036f4609 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -306,10 +307,51 @@ static void *etb_setup_aux(struct coresight_device *csdev, int cpu, return buf; } +static int etb_set_buffer(struct coresight_device *csdev, + struct perf_event *event, + struct perf_output_handle *handle) +{ + unsigned long head; + struct cs_buffers *buf; + + buf = perf_aux_output_begin(handle, event); + if (!buf) + return -EINVAL; + + /* how much space do we have in this session */ + buf->size = handle->size; + + /* wrap head around to the amount of space we have */ + head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + + /* find the page to write to */ + buf->cur = head / PAGE_SIZE; + + /* and offset within that page */ + buf->offset = head % PAGE_SIZE; + + local_set(&buf->head, head); + local_set(&buf->data_size, 0); + + return 0; +} + +static void etb_unset_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle) +{ + struct cs_buffers *buf = perf_get_aux(handle); + + if (buf) + perf_aux_output_end(handle, local_xchg(&buf->data_size, 0), + local_xchg(&buf->lost, 0)); +} + static const struct coresight_ops_sink etb_sink_ops = { .enable = etb_enable, .disable = etb_disable, .setup_aux = etb_setup_aux, + .set_buffer = etb_set_buffer, + .unset_buffer = etb_unset_buffer, }; static const struct coresight_ops etb_cs_ops = { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 71cc23709422..25bdce345ec3 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -15,6 +15,7 @@ #include #include +#include /* Peripheral id registers (0xFD0-0xFEC) */ #define CORESIGHT_PERIPHIDR4 0xfd0 @@ -186,12 +187,19 @@ struct coresight_device { * @enable: enables the sink. * @disable: disables the sink. * @setup_aux: initialises perf's ring buffer for trace collection. + * @set_buffer: initialises buffer mechanic before a trace session. + * @unset_buffer: finalises buffer mechanic after a trace session. */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev); void (*disable)(struct coresight_device *csdev); void *(*setup_aux)(struct coresight_device *csdev, int cpu, void **pages, int nr_pages, bool overwrite); + int (*set_buffer)(struct coresight_device *csdev, + struct perf_event *event, + struct perf_output_handle *handle); + void (*unset_buffer)(struct coresight_device *csdev, + struct perf_output_handle *handle); }; /**