From patchwork Sun Oct 18 18:24:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 55186 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f199.google.com (mail-lb0-f199.google.com [209.85.217.199]) by patches.linaro.org (Postfix) with ESMTPS id 3475522FFA for ; Sun, 18 Oct 2015 18:26:02 +0000 (UTC) Received: by lbbms9 with SMTP id ms9sf37781808lbb.3 for ; Sun, 18 Oct 2015 11:26:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=F73s3ICDs7SzIKZrEBB1ofxBsyyeI6IXo/5gSqsC2+c=; b=co6inMe/TosGNcyBjql1fLnjSnJXicuftYXbfEfQi0XNyMRwFc59X/G2FljqapfBY+ nz5Eu9yPSB3p1I/8HQ/IOigkedzXBnkzszevinXsfCkePqhlv+UnQ5uVVp7LFy3qN4BD rtT4iTc5fS44pD5YFxriMYeMbdZ0AtrXDB80Egit+smiYdnCUZpil4q0IAqjp+E+7gbp Ht8Oxge1BwEyzq/axoIsS4tyTFn2IMDBQRZSdSdKcaOh1oa4rLxD8YBJfCKvaCuUMWwt NYG72yMYFi40w3NWlM74lRpkGYkF/k0VZyU25yOGbXhgIG7E//QjVIv2eXZPwtrIAP2s S6cw== X-Gm-Message-State: ALoCoQnEkkxX2c2zLKY90o99n1gfqYHjrwBhONgv1xOYbZH3G2HtTnayU8ChFPjWAL1d6izA/GbD X-Received: by 10.180.105.98 with SMTP id gl2mr3497709wib.0.1445192760961; Sun, 18 Oct 2015 11:26:00 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.25.21.77 with SMTP id l74ls522312lfi.20.gmail; Sun, 18 Oct 2015 11:26:00 -0700 (PDT) X-Received: by 10.112.150.201 with SMTP id uk9mr12923132lbb.102.1445192760787; Sun, 18 Oct 2015 11:26:00 -0700 (PDT) Received: from mail-lf0-f53.google.com (mail-lf0-f53.google.com. [209.85.215.53]) by mx.google.com with ESMTPS id s20si20103965lfe.134.2015.10.18.11.26.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 18 Oct 2015 11:26:00 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) client-ip=209.85.215.53; Received: by lfaz124 with SMTP id z124so97487362lfa.1 for ; Sun, 18 Oct 2015 11:26:00 -0700 (PDT) X-Received: by 10.25.19.97 with SMTP id j94mr8505028lfi.106.1445192760665; Sun, 18 Oct 2015 11:26:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1077940lbq; Sun, 18 Oct 2015 11:25:59 -0700 (PDT) X-Received: by 10.66.228.97 with SMTP id sh1mr29371626pac.91.1445192752725; Sun, 18 Oct 2015 11:25:52 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id yk2si46418601pac.192.2015.10.18.11.25.52; Sun, 18 Oct 2015 11:25:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752248AbbJRSZs (ORCPT + 28 others); Sun, 18 Oct 2015 14:25:48 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:34336 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751762AbbJRSZp (ORCPT ); Sun, 18 Oct 2015 14:25:45 -0400 Received: by padhk11 with SMTP id hk11so6278312pad.1 for ; Sun, 18 Oct 2015 11:25:45 -0700 (PDT) X-Received: by 10.68.184.5 with SMTP id eq5mr30034740pbc.130.1445192745528; Sun, 18 Oct 2015 11:25:45 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [184.64.168.246]) by smtp.gmail.com with ESMTPSA id hq1sm20402076pbb.43.2015.10.18.11.25.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Oct 2015 11:25:45 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org Subject: [PATCH V2 10/30] coresight: etm3x: consolidating initial config Date: Sun, 18 Oct 2015 12:24:27 -0600 Message-Id: <1445192687-24112-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> References: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , There is really no point having two functions to take care of doing the initials tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++----------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 8bd161584f85..cc0b08437419 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); /* The number of ETM/PTM currently registered */ static int etm_count; static struct etm_drvdata *etmdrvdata[NR_CPUS]; -static void etm_init_default_data(struct etm_config *config); /* * Memory mapped writes to clear os lock are not supported on some processors @@ -199,7 +198,7 @@ struct etm_config *get_etm_config(struct etm_drvdata *drvdata) return NULL; /* Set default config */ - etm_init_default_data(config); + etm_set_default(config); drvdata->config = config; out: return drvdata->config; @@ -212,6 +211,19 @@ void etm_set_default(struct etm_config *config) if (WARN_ON_ONCE(!config)) return; + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; + config->trigger_event = ETM_DEFAULT_EVENT_VAL; config->enable_event = ETM_HARD_WIRE_RES_A; @@ -565,27 +577,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_default_data(struct etm_config *config) -{ - if (WARN_ON_ONCE(!config)) - return; - - etm_set_default(config); - - /* - * Taken verbatim from the TRM: - * - * To trace all memory: - * set bit [24] in register 0x009, the ETMTECR1, to 1 - * set all other bits in register 0x009, the ETMTECR1, to 0 - * set all bits in register 0x007, the ETMTECR2, to 0 - * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). - */ - config->enable_ctrl1 = BIT(24); - config->enable_ctrl2 = 0x0; - config->enable_event = ETM_HARD_WIRE_RES_A; -} - static void etm_init_trace_id(struct etm_drvdata *drvdata) { /*