From patchwork Thu Dec 3 06:11:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57618 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp3318685lbb; Wed, 2 Dec 2015 22:31:53 -0800 (PST) X-Received: by 10.98.9.88 with SMTP id e85mr10729858pfd.7.1449124313183; Wed, 02 Dec 2015 22:31:53 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id fu6si9891899pac.175.2015.12.02.22.31.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Dec 2015 22:31:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NPM-0000p6-Qe; Thu, 03 Dec 2015 06:30:24 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NOE-0006zY-TC for linux-arm-kernel@lists.infradead.org; Thu, 03 Dec 2015 06:29:20 +0000 Received: from 172.24.1.51 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.51]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CXG85937; Thu, 03 Dec 2015 14:12:39 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 3 Dec 2015 14:12:27 +0800 From: Shannon Zhao To: , , Subject: [PATCH v5 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Date: Thu, 3 Dec 2015 14:11:23 +0800 Message-ID: <1449123091-20252-14-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> References: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.565FDD57.0078, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3cd13b50345593957069703bb632c8c3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151202_222915_761493_25BE601E X-CRM114-Status: GOOD ( 17.58 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [119.145.14.65 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, pend PMU interrupt. When the value writing to PMOVSCLR is equal to the current value, clear the PMU pending interrupt. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 25 +++++++++++++-- include/kvm/arm_pmu.h | 4 +++ virt/kvm/arm/pmu.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 3 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a4f9177..f5e0732 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -559,6 +559,14 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; break; } + case PMOVSSET_EL0: { + kvm_pmu_overflow_set(vcpu, *vcpu_reg(vcpu, p->Rt)); + break; + } + case PMOVSCLR_EL0: { + kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt)); + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -803,7 +811,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 }, /* PMOVSCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMOVSCLR_EL0 }, /* PMSWINC_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), trap_raz_wi }, @@ -830,7 +838,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { trap_raz_wi }, /* PMOVSSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMOVSSET_EL0 }, /* TPIDR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010), @@ -1103,6 +1111,14 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val; break; } + case c9_PMOVSSET: { + kvm_pmu_overflow_set(vcpu, *vcpu_reg(vcpu, p->Rt)); + break; + } + case c9_PMOVSCLR: { + kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt)); + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1188,7 +1204,8 @@ static const struct sys_reg_desc cp15_regs[] = { NULL, c9_PMCNTENSET }, { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs, NULL, c9_PMCNTENCLR }, - { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs, + NULL, c9_PMOVSCLR }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, NULL, c9_PMSELR }, { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs, @@ -1206,6 +1223,8 @@ static const struct sys_reg_desc cp15_regs[] = { NULL, c9_PMINTENSET }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs, NULL, c9_PMINTENCLR }, + { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmu_cp15_regs, + NULL, c9_PMOVSSET }, { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index fff8f15..4f3154c 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -42,6 +42,8 @@ struct kvm_pmu { unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx); void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable); +void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val); +void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); #else @@ -51,6 +53,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) } void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {} +void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) {} +void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 0d143ca..296b4ad 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -125,6 +125,86 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) } } +static unsigned long kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) +{ + u32 val; + + if (!vcpu_mode_is_32bit(vcpu)) + val = (vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMCR_N_SHIFT) + & ARMV8_PMCR_N_MASK; + else + val = (vcpu_cp15(vcpu, c9_PMCR) >> ARMV8_PMCR_N_SHIFT) + & ARMV8_PMCR_N_MASK; + + return GENMASK(val - 1, 0) | BIT(ARMV8_COUNTER_MASK); +} + +/** + * kvm_pmu_overflow_clear - clear PMU overflow interrupt + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMOVSCLR register + * @reg: the current value of PMOVSCLR register + */ +void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) +{ + u32 mask = kvm_pmu_valid_counter_mask(vcpu); + + if (!vcpu_mode_is_32bit(vcpu)) { + vcpu_sys_reg(vcpu, PMOVSCLR_EL0) &= mask; + vcpu_sys_reg(vcpu, PMOVSCLR_EL0) &= ~val; + vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask; + vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~val; + val = vcpu_sys_reg(vcpu, PMOVSSET_EL0); + } else { + vcpu_cp15(vcpu, c9_PMOVSCLR) &= mask; + vcpu_cp15(vcpu, c9_PMOVSCLR) &= ~val; + vcpu_cp15(vcpu, c9_PMOVSSET) &= mask; + vcpu_cp15(vcpu, c9_PMOVSSET) &= ~val; + val = vcpu_cp15(vcpu, c9_PMOVSSET); + } + + /* If all overflow bits are cleared, kick the vcpu to clear interrupt + * pending status. + */ + if (val == 0) + kvm_vcpu_kick(vcpu); +} + +/** + * kvm_pmu_overflow_set - set PMU overflow interrupt + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMOVSSET register + */ +void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) +{ + u32 mask = kvm_pmu_valid_counter_mask(vcpu); + + val &= mask; + if (val == 0) + return; + + if (!vcpu_mode_is_32bit(vcpu)) { + vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask; + vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= val; + vcpu_sys_reg(vcpu, PMOVSCLR_EL0) &= mask; + vcpu_sys_reg(vcpu, PMOVSCLR_EL0) |= val; + val = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) + & vcpu_sys_reg(vcpu, PMINTENSET_EL1) + & vcpu_sys_reg(vcpu, PMOVSSET_EL0); + } else { + vcpu_cp15(vcpu, c9_PMOVSSET) &= mask; + vcpu_cp15(vcpu, c9_PMOVSSET) |= val; + vcpu_cp15(vcpu, c9_PMOVSCLR) &= mask; + vcpu_cp15(vcpu, c9_PMOVSCLR) |= val; + val = vcpu_cp15(vcpu, c9_PMCNTENSET) + & vcpu_cp15(vcpu, c9_PMINTENSET) + & vcpu_cp15(vcpu, c9_PMOVSSET); + } + + if (val != 0) + kvm_vcpu_kick(vcpu); +} + /** * kvm_pmu_set_counter_event_type - set selected counter to monitor some event * @vcpu: The vcpu pointer