From patchwork Tue Dec 8 12:47:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57849 Delivered-To: patch@linaro.org Received: by 10.112.147.194 with SMTP id tm2csp6630lbb; Tue, 8 Dec 2015 04:53:05 -0800 (PST) X-Received: by 10.66.193.73 with SMTP id hm9mr4123366pac.117.1449579185183; Tue, 08 Dec 2015 04:53:05 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id bz5si5194410pab.12.2015.12.08.04.53.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2015 04:53:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6Hjv-0001ta-6T; Tue, 08 Dec 2015 12:51:31 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6HiG-0006zS-W7 for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 12:50:02 +0000 Received: from 172.24.1.50 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.50]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CXQ74808; Tue, 08 Dec 2015 20:48:22 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Tue, 8 Dec 2015 20:48:14 +0800 From: Shannon Zhao To: , , Subject: [PATCH v6 12/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Date: Tue, 8 Dec 2015 20:47:31 +0800 Message-ID: <1449578860-15808-13-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> References: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5666D196.0153, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b00b98417fb4184de700afc85df9d528 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151208_044950_892531_5E4421FC X-CRM114-Status: GOOD ( 17.50 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [119.145.14.65 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR, call perf_event_disable to disable the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 39 +++++++++++++++++++++++++++++++++++---- include/kvm/arm_pmu.h | 4 ++++ virt/kvm/arm/pmu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 4 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2304937..a780cb5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -577,6 +577,21 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, r->reg) = p->regval; break; } + case PMCNTENSET_EL0: { + val = p->regval; + if (r->Op2 == 1) { + /* accessing PMCNTENSET_EL0 */ + kvm_pmu_enable_counter(vcpu, val, + vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E); + vcpu_sys_reg(vcpu, r->reg) |= val; + } else { + + /* accessing PMCNTENCLR_EL0 */ + kvm_pmu_disable_counter(vcpu, val); + vcpu_sys_reg(vcpu, r->reg) &= ~val; + } + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -817,10 +832,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_pmcr, PMCR_EL0, }, /* PMCNTENSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCNTENSET_EL0 }, /* PMCNTENCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCNTENSET_EL0 }, /* PMOVSCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), trap_raz_wi }, @@ -1137,6 +1152,20 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, r->reg) = p->regval; break; } + case c9_PMCNTENSET: { + val = p->regval; + if (r->Op2 == 1) { + /* accessing c9_PMCNTENSET */ + kvm_pmu_enable_counter(vcpu, val, + vcpu_cp15(vcpu, c9_PMCR) & ARMV8_PMCR_E); + vcpu_cp15(vcpu, r->reg) |= val; + } else { + /* accessing c9_PMCNTENCLR */ + kvm_pmu_disable_counter(vcpu, val); + vcpu_cp15(vcpu, r->reg) &= ~val; + } + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1220,8 +1249,10 @@ static const struct sys_reg_desc cp15_regs[] = { /* PMU */ { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs, NULL, c9_PMCR }, - { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs, + NULL, c9_PMCNTENSET }, + { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs, + NULL, c9_PMCNTENSET }, { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, NULL, c9_PMSELR }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 36bde48..e731656 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -39,6 +39,8 @@ struct kvm_pmu { #ifdef CONFIG_KVM_ARM_PMU u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx); +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); #else @@ -46,6 +48,8 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) { return 0; } +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {} +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 15babf1..45586d2 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -90,6 +90,53 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc) } /** + * kvm_pmu_enable_counter - enable selected PMU counter + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCNTENSET register + * @all_enable: the value of PMCR.E + * + * Call perf_event_enable to start counting the perf event + */ +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) +{ + int i; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + + if (!all_enable) + return; + + for_each_set_bit(i, (const unsigned long *)&val, ARMV8_MAX_COUNTERS) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) { + perf_event_enable(pmc->perf_event); + if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE) + kvm_debug("fail to enable perf event\n"); + } + } +} + +/** + * kvm_pmu_disable_counter - disable selected PMU counter + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCNTENCLR register + * + * Call perf_event_disable to stop counting the perf event + */ +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) +{ + int i; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + + for_each_set_bit(i, (const unsigned long *)&val, ARMV8_MAX_COUNTERS) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) + perf_event_disable(pmc->perf_event); + } +} + +/** * kvm_pmu_set_counter_event_type - set selected counter to monitor some event * @vcpu: The vcpu pointer * @data: The data guest writes to PMXEVTYPER_EL0