From patchwork Mon Nov 28 16:59:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rabin Vincent X-Patchwork-Id: 5323 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8125E23E03 for ; Mon, 28 Nov 2011 17:00:03 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id 3D8ACA18303 for ; Mon, 28 Nov 2011 17:00:03 +0000 (UTC) Received: by laah2 with SMTP id h2so861992laa.11 for ; Mon, 28 Nov 2011 09:00:02 -0800 (PST) Received: by 10.152.110.130 with SMTP id ia2mr7841443lab.26.1322499602871; Mon, 28 Nov 2011 09:00:02 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs450502lal; Mon, 28 Nov 2011 08:59:59 -0800 (PST) Received: by 10.50.169.38 with SMTP id ab6mr51318142igc.26.1322499596675; Mon, 28 Nov 2011 08:59:56 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id o10si19478926icv.111.2011.11.28.08.59.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 28 Nov 2011 08:59:56 -0800 (PST) Received-SPF: pass (google.com: domain of rabin.vincent@gmail.com designates 209.85.210.178 as permitted sender) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of rabin.vincent@gmail.com designates 209.85.210.178 as permitted sender) smtp.mail=rabin.vincent@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by iadj38 with SMTP id j38so11120227iad.37 for ; Mon, 28 Nov 2011 08:59:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type :content-transfer-encoding; bh=W+slUVjsGN8EF/DssoExHYeHOGcC6KsaQoCJPWogVRE=; b=EHau8F1CE0rssnofBaQ360rUrbjvdPzwPLuFNj4CS+NAuCqPm7SvVcKo7ycZLrmY5Q QPN/ADNF8MuHle8WkIXOsLlZNxYsZNaI94TVJTz+8XEpJVtx8p1DQjd9Kr1MBzScTu2K QZkKE7PZDhQycfKiICimwQVgmvFMyQ0rU3al8= Received: by 10.231.5.215 with SMTP id 23mr3035024ibw.83.1322499595121; Mon, 28 Nov 2011 08:59:55 -0800 (PST) MIME-Version: 1.0 Sender: rabin.vincent@gmail.com Received: by 10.50.6.228 with HTTP; Mon, 28 Nov 2011 08:59:14 -0800 (PST) In-Reply-To: <1322220493-3251-1-git-send-email-dave.martin@linaro.org> References: <1322220493-3251-1-git-send-email-dave.martin@linaro.org> From: Rabin Vincent Date: Mon, 28 Nov 2011 22:29:14 +0530 X-Google-Sender-Auth: _2X7gFWlSNELEHPS6v49yipQZbs Message-ID: Subject: Re: [RFC PATCH] ARM: Add generic instruction opcode manipulation helpers To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org, Bi Junxiao , Tixy On Fri, Nov 25, 2011 at 16:58, Dave Martin wrote: > +#ifdef CONFIG_CPU_ENDIAN_BE8 > +#define __opcode_to_mem_arm(x) swab32(x) > +#define __opcode_to_mem_thumb16(x) swab16(x) > +#define __opcode_to_mem_thumb32(x) swahb32(x) > +#else > +#define __opcode_to_mem_arm(x) (x) ((u32)(x)) > +#define __opcode_to_mem_thumb16(x) ((u16)(x)) > +#define __opcode_to_mem_thumb32(x) swahw32(x) > +#endif The current kprobes code does: #ifndef __ARMEB__ /* Swap halfwords for little-endian */ bkp = (bkp >> 16) | (bkp << 16); #endif There seems to be a difference between your macros and that for the case __ARMEB__ + !CONFIG_CPU_ENDIAN_BE8. Or is that combination not possible? > + > +#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) > +#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) > +#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) > + > +/* Operations specific to Thumb opcodes */ > + > +/* Instruction size checks: */ > +#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL) > +#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL) > + > +/* Operations to construct or split 32-bit Thumb instructions: */ > +#define __opcode_thumb32_first(x) ((u16)((thumb_opcode) >> 16)) > +#define __opcode_thumb32_second(x) ((u16)(thumb_opcode)) > +#define __opcode_thumb32_compose(first, second) \ > +       (((u32)(u16)(first) << 16) | (u32)(u16)(second)) All of these could certainly find use in the files being touched by the jump label patchset: diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index c46d18b..c437a9d 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -72,12 +72,13 @@ static int ftrace_modify_code(unsigned long pc, unsigned long old, { unsigned long replaced; -#ifndef __ARMEB__ if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) { - old = (old >> 16) | (old << 16); - new = (new >> 16) | (new << 16); + old = __opcode_to_mem_thumb32(old); + new = __opcode_to_mem_thumb32(new); + } else { + old = __opcode_to_mem_arm(old); + new = __opcode_to_mem_arm(new); } -#endif if (old) { if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE)) diff --git a/arch/arm/kernel/insn.c b/arch/arm/kernel/insn.c index f65b68c..9079997 100644 --- a/arch/arm/kernel/insn.c +++ b/arch/arm/kernel/insn.c @@ -27,7 +27,7 @@ __arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link) if (link) second |= 1 << 14; - return (first << 16) | second; + return __opcode_thumb32_compose(first, second); } static unsigned long diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c index 15df8a5..5398659 100644 --- a/arch/arm/kernel/patch.c +++ b/arch/arm/kernel/patch.c @@ -17,21 +17,21 @@ void __kprobes __patch_text(void *addr, unsigned int insn) bool thumb2 = IS_ENABLED(CONFIG_THUMB2_KERNEL); int size; - if (thumb2 && !is_wide_instruction(insn)) { - *(u16 *)addr = insn; + if (thumb2 && __opcode_is_thumb16(insn)) { + *(u16 *)addr = __opcode_to_mem_thumb16(insn); size = sizeof(u16); } else if (thumb2 && ((uintptr_t)addr & 2)) { u16 *addrh = addr; - addrw[0] = insn >> 16; - addrw[1] = insn & 0xffff; + addrw[0] = __opcode_thumb32_first(insn); + addrw[1] = __opcode_thumb32_second(insn); size = sizeof(u32); } else { -#ifndef __ARMEB__ if (thumb2) - insn = (insn >> 16) | (insn << 16); -#endif + insn = __opcode_to_mem_thumb32(insn); + else + insn = __opcode_to_mem_arm(insn); *(u32 *)addr = insn; size = sizeof(u32); @@ -61,7 +61,7 @@ void __kprobes patch_text(void *addr, unsigned int insn) stop_machine(patch_text_stop_machine, &patch, cpu_online_mask); } else { bool straddles_word = IS_ENABLED(CONFIG_THUMB2_KERNEL) - && is_wide_instruction(insn) + && __opcode_is_thumb32(insn) && ((uintptr_t)addr & 2); if (straddles_word)