| Message ID | 20200810222657.1841322-1-jcrouse@codeaurora.org |
|---|---|
| Headers | show |
| Series | iommu/arm-smmu: Add Adreno SMMU specific implementation | expand |
On Mon, Aug 10, 2020 at 04:26:48PM -0600, Jordan Crouse wrote: > Add domain attribute DOMAIN_ATTR_PGTABLE_CFG. This will be used by > arm-smmu to share the current pagetable configuration with the > leaf driver and to allow the leaf driver to set up a new pagetable > configuration under certain circumstances. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > include/linux/iommu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index fee209efb756..995ab8c47ef2 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -118,6 +118,7 @@ enum iommu_attr { > DOMAIN_ATTR_FSL_PAMUV1, > DOMAIN_ATTR_NESTING, /* two stages of translation */ > DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > + DOMAIN_ATTR_PGTABLE_CFG, > DOMAIN_ATTR_MAX, > }; Nobody other than the adreno gpu uses this, so can we avoid exposing it in the IOMMU API, please? Given that you have a reference to the adreno GPU device in the SMMU implementation code thanks to .alloc_context_bank(), can you squirrel some function pointers away in the driver data (i.e. with dev_set_drvdata()) instead? Will
On Thu, Aug 13, 2020 at 6:14 AM Will Deacon <will@kernel.org> wrote: > > On Mon, Aug 10, 2020 at 04:26:48PM -0600, Jordan Crouse wrote: > > Add domain attribute DOMAIN_ATTR_PGTABLE_CFG. This will be used by > > arm-smmu to share the current pagetable configuration with the > > leaf driver and to allow the leaf driver to set up a new pagetable > > configuration under certain circumstances. > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > --- > > > > include/linux/iommu.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > > index fee209efb756..995ab8c47ef2 100644 > > --- a/include/linux/iommu.h > > +++ b/include/linux/iommu.h > > @@ -118,6 +118,7 @@ enum iommu_attr { > > DOMAIN_ATTR_FSL_PAMUV1, > > DOMAIN_ATTR_NESTING, /* two stages of translation */ > > DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > > + DOMAIN_ATTR_PGTABLE_CFG, > > DOMAIN_ATTR_MAX, > > }; > > Nobody other than the adreno gpu uses this, so can we avoid exposing it > in the IOMMU API, please? Given that you have a reference to the adreno > GPU device in the SMMU implementation code thanks to .alloc_context_bank(), > can you squirrel some function pointers away in the driver data (i.e. with > dev_set_drvdata()) instead? > Hmm, we are already using drvdata on the gpu side, and it looks like arm-smmu is also using it. Could we get away with stashing an extra 'void *' in iommu_domain itself? Or alternatively, if we had a is_arm_smmu_domain(domain), then we could just directly call some exported private fxns with the domain ptr (which could then verify that the domain is actually an arm_smmu_domain, and then from there that the smmu is indeed qcom,adreno-smmu, to keep things sane) BR, -R
On Mon, Aug 10, 2020 at 3:27 PM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > Each submitqueue is attached to a context. Add a pointer to the > context to the submitqueue at create time and refcount it so > that it stays around through the life of the queue. > > GPU submissions can access the active context via the submitqueue > instead of requiring it to be passed around from function to > function. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++++------- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++--- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++--- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- > drivers/gpu/drm/msm/msm_drv.c | 3 ++- > drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++ > drivers/gpu/drm/msm/msm_gem.h | 1 + > drivers/gpu/drm/msm/msm_gem_submit.c | 8 ++++---- > drivers/gpu/drm/msm/msm_gpu.c | 9 ++++----- > drivers/gpu/drm/msm/msm_gpu.h | 7 +++---- > drivers/gpu/drm/msm/msm_submitqueue.c | 8 +++++++- > 11 files changed, 39 insertions(+), 30 deletions(-) > [snip] > diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h > index 972490b14ba5..9c573c4269cb 100644 > --- a/drivers/gpu/drm/msm/msm_gem.h > +++ b/drivers/gpu/drm/msm/msm_gem.h > @@ -142,6 +142,7 @@ struct msm_gem_submit { > bool valid; /* true if no cmdstream patching needed */ > bool in_rb; /* "sudo" mode, copy cmds into RB */ > struct msm_ringbuffer *ring; > + struct msm_file_private *ctx; So, it looks like this is (currently) unused, and everything is instead using submit->queue->ctx That said, changing this so the submit also holds a ref to the ctx seems to fix the intermittent splat I can trigger by repeatedly hanging the gpu. Which (from the pile of additional tracepoints I've added on top of this series) seems to be related to re-playing submits after the userspace process has crashed and/or closed the device. It seems like the reference the submit holds to the queue should keep the ctx (and therefore address space) alive, but I need to dig through that a bit more. BR, -R > unsigned int nr_cmds; > unsigned int nr_bos; > u32 ident; /* A "identifier" for the submit for logging */
On Mon, Aug 10, 2020 at 3:27 PM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > Each submitqueue is attached to a context. Add a pointer to the > context to the submitqueue at create time and refcount it so > that it stays around through the life of the queue. > > GPU submissions can access the active context via the submitqueue > instead of requiring it to be passed around from function to > function. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++++------- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++--- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++--- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- > drivers/gpu/drm/msm/msm_drv.c | 3 ++- > drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++ > drivers/gpu/drm/msm/msm_gem.h | 1 + > drivers/gpu/drm/msm/msm_gem_submit.c | 8 ++++---- > drivers/gpu/drm/msm/msm_gpu.c | 9 ++++----- > drivers/gpu/drm/msm/msm_gpu.h | 7 +++---- > drivers/gpu/drm/msm/msm_submitqueue.c | 8 +++++++- > 11 files changed, 39 insertions(+), 30 deletions(-) > [snip] > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > index a1d94be7883a..10f557225a3e 100644 > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) > * No lock needed in close and there won't > * be any more user ioctls coming our way > */ > - list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) > + list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) { > + kref_put(&ctx->ref, msm_file_private_destroy); > msm_submitqueue_put(entry); > + } oh, this is the problem I mentioned in the last email.. we are dropping the queue's reference to the ctx, when the device file is closed, not on the last unref of the queue. So the queue stays live until all associated submits are retired, but the ctx ref (and therefore the aspace) get destroyed earlier BR, -R > } > > int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
From: Rob Clark <robdclark@chromium.org>
NOTE: Since Jordan was out today, and I wanted to keep things moving on
this, I took the liberty of respinning his series (originally
titled "iommu/arm-smmu: Add Adreno SMMU specific implementation")
with updates based on Will's review comments, and some fixes and
extra bits that I found in stress testing the series. Original
commit msg and updated version history below.
In general I like the private interface between adreno-smmu and
the GPU driver. It should make for a more straightforward way
to extend things to optimize TLB invalidation in the future, for
example, rather than shoe-horning everything thru domain attrs.
And it lets us describe the get_ttbr1_cfg/set_ttrb0_cfg dance
more clearly. Although it is going to make landing this via
iommu vs drm tree a bit more difficult. Maybe there are some
arm-smmu parts of this series that could be pulled out to make
it not conflicty to land the private interface and adreno-smmu
bits via the drm tree? (But I'm jumping a bit ahead here. Just
wanted to point out that issue.)
The complete series can be found at:
https://gitlab.freedesktop.org/drm/msm/-/commits/msm-next-pgtables
This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware
pagetable switching.
The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during
runtime to allow each individual instance or application to have its own
pagetable. In order to take advantage of the HW capabilities there are certain
requirements needed of the SMMU hardware.
This series adds support for an Adreno specific arm-smmu implementation. The new
implementation 1) ensures that the GPU domain is always assigned context bank 0,
2) enables split pagetable support (TTBR1) so that the instance specific
pagetable can be swapped while the global memory remains in place and 3) shares
the current pagetable configuration with the GPU driver to allow it to create
its own io-pgtable instances.
The series then adds the drm/msm code to enable these features. For targets that
support it allocate new pagetables using the io-pgtable configuration shared by
the arm-smmu driver and swap them in during runtime.
This version of the series merges the previous patchset(s) [1] and [2]
with the following improvements:
v13: (Respin by Rob)
- Switch to a private interface between adreno-smmu and GPU driver,
dropping the custom domain attr (Will Deacon)
- Rework the SCTLR.HUPCF patch to add new fields in smmu_domain->cfg
rather than adding new impl hook (Will Deacon)
- Drop for_each_cfg_sme() in favor of plain for() loop (Will Deacon)
- Fix context refcnt'ing issue which was causing problems with GPU
crash recover stress testing.
- Spiff up $debugfs/gem to show process information associated with
VMAs
v12:
- Nitpick cleanups in gpu/drm/msm/msm_iommu.c (Rob Clark)
- Reorg in gpu/drm/msm/msm_gpu.c (Rob Clark)
- Use the default asid for the context bank so that iommu_tlb_flush_all works
- Flush the UCHE after a page switch
- Add the SCTLR.HUPCF patch at the end of the series
v11:
- Add implementation specific get_attr/set_attr functions (per Rob Clark)
- Fix context bank allocation (per Bjorn Andersson)
v10:
- arm-smmu: add implementation hook to allocate context banks
- arm-smmu: Match the GPU domain by stream ID instead of compatible string
- arm-smmu: Make DOMAIN_ATTR_PGTABLE_CFG bi-directional. The leaf driver
queries the configuration to create a pagetable and then sends the newly
created configuration back to the smmu-driver to enable TTBR0
- drm/msm: Add context reference counting for submissions
- drm/msm: Use dummy functions to skip TLB operations on per-instance
pagetables
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045653.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html
Jordan Crouse (12):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add support for split pagetables
iommu/arm-smmu: Prepare for the adreno-smmu implementation
iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU
dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
drm/msm: Add a context pointer to the submitqueue
drm/msm: Drop context arg to gpu->submit()
drm/msm: Set the global virtual address range from the IOMMU domain
drm/msm: Add support to create a local pagetable
drm/msm: Add support for private address space instances
drm/msm/a6xx: Add support for per-instance pagetables
arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU
Rob Clark (7):
drm/msm: remove dangling submitqueue references
iommu: add private interface for adreno-smmu
drm/msm/gpu: add dev_to_gpu() helper
drm/msm: set adreno_smmu as gpu's drvdata
iommu/arm-smmu: constify some helpers
iommu/arm-smmu: add a way for implementations to influence SCTLR
drm/msm: show process names in gem_describe
.../devicetree/bindings/iommu/arm,smmu.yaml | 4 +
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 75 ++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/adreno/adreno_device.c | 12 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-
drivers/gpu/drm/msm/msm_drv.c | 16 +-
drivers/gpu/drm/msm/msm_drv.h | 25 +++
drivers/gpu/drm/msm/msm_gem.c | 25 ++-
drivers/gpu/drm/msm/msm_gem.h | 6 +
drivers/gpu/drm/msm/msm_gem_submit.c | 8 +-
drivers/gpu/drm/msm/msm_gem_vma.c | 10 +
drivers/gpu/drm/msm/msm_gpu.c | 41 +++-
drivers/gpu/drm/msm/msm_gpu.h | 21 +-
drivers/gpu/drm/msm/msm_gpummu.c | 2 +-
drivers/gpu/drm/msm/msm_iommu.c | 206 +++++++++++++++++-
drivers/gpu/drm/msm/msm_mmu.h | 16 +-
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
drivers/gpu/drm/msm/msm_submitqueue.c | 7 +-
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 6 +-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 155 ++++++++++++-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 102 ++++-----
drivers/iommu/arm/arm-smmu/arm-smmu.h | 87 +++++++-
include/linux/adreno-smmu-priv.h | 36 +++
26 files changed, 765 insertions(+), 132 deletions(-)
create mode 100644 include/linux/adreno-smmu-priv.h
On Thu, Aug 13, 2020 at 07:40:56PM -0700, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > Currently it doesn't matter, since we free the ctx immediately. But > when we start refcnt'ing the ctx, we don't want old dangling list > entries to hang around. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > index a1d94be7883a..90c9d84e6155 100644 > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) > * No lock needed in close and there won't > * be any more user ioctls coming our way > */ > - list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) > + list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) { > + list_del(&entry->node); > msm_submitqueue_put(entry); > + } > } > > int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, > -- > 2.26.2 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu
On Thu, Aug 13, 2020 at 07:41:14PM -0700, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > In $debugfs/gem we already show any vma(s) associated with an object. > Also show process names if the vma's address space is a per-process > address space. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_drv.c | 2 +- > drivers/gpu/drm/msm/msm_gem.c | 25 +++++++++++++++++++++---- > drivers/gpu/drm/msm/msm_gem.h | 5 +++++ > drivers/gpu/drm/msm/msm_gem_vma.c | 1 + > drivers/gpu/drm/msm/msm_gpu.c | 8 +++++--- > drivers/gpu/drm/msm/msm_gpu.h | 2 +- > 6 files changed, 34 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c > index 8e70d220bba8..8d5c4f98c332 100644 > --- a/drivers/gpu/drm/msm/msm_drv.c > +++ b/drivers/gpu/drm/msm/msm_drv.c > @@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) > kref_init(&ctx->ref); > msm_submitqueue_init(dev, ctx); > > - ctx->aspace = msm_gpu_create_private_address_space(priv->gpu); > + ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); > file->driver_priv = ctx; > > return 0; > diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c > index 3cb7aeb93fd3..76a6c5271e57 100644 > --- a/drivers/gpu/drm/msm/msm_gem.c > +++ b/drivers/gpu/drm/msm/msm_gem.c > @@ -842,11 +842,28 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m) > > seq_puts(m, " vmas:"); > > - list_for_each_entry(vma, &msm_obj->vmas, list) > - seq_printf(m, " [%s: %08llx,%s,inuse=%d]", > - vma->aspace != NULL ? vma->aspace->name : NULL, > - vma->iova, vma->mapped ? "mapped" : "unmapped", > + list_for_each_entry(vma, &msm_obj->vmas, list) { > + const char *name, *comm; > + if (vma->aspace) { > + struct msm_gem_address_space *aspace = vma->aspace; > + struct task_struct *task = > + get_pid_task(aspace->pid, PIDTYPE_PID); > + if (task) { > + comm = kstrdup(task->comm, GFP_KERNEL); > + } else { > + comm = NULL; > + } > + name = aspace->name; > + } else { > + name = comm = NULL; > + } > + seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s,inuse=%d]", > + name, comm ? ":" : "", comm ? comm : "", > + vma->aspace, vma->iova, > + vma->mapped ? "mapped" : "unmapped", > vma->inuse); > + kfree(comm); > + } > > seq_puts(m, "\n"); > } > diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h > index 9c573c4269cb..7b1c7a5f8eef 100644 > --- a/drivers/gpu/drm/msm/msm_gem.h > +++ b/drivers/gpu/drm/msm/msm_gem.h > @@ -24,6 +24,11 @@ struct msm_gem_address_space { > spinlock_t lock; /* Protects drm_mm node allocation/removal */ > struct msm_mmu *mmu; > struct kref kref; > + > + /* For address spaces associated with a specific process, this > + * will be non-NULL: > + */ > + struct pid *pid; > }; > > struct msm_gem_vma { > diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c > index 29cc1305cf37..80a8a266d68f 100644 > --- a/drivers/gpu/drm/msm/msm_gem_vma.c > +++ b/drivers/gpu/drm/msm/msm_gem_vma.c > @@ -17,6 +17,7 @@ msm_gem_address_space_destroy(struct kref *kref) > drm_mm_takedown(&aspace->mm); > if (aspace->mmu) > aspace->mmu->funcs->destroy(aspace->mmu); > + put_pid(aspace->pid); > kfree(aspace); > } > > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 951850804d77..ac8961187a73 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -825,10 +825,9 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) > > /* Return a new address space for a msm_drm_private instance */ > struct msm_gem_address_space * > -msm_gpu_create_private_address_space(struct msm_gpu *gpu) > +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) > { > struct msm_gem_address_space *aspace = NULL; > - > if (!gpu) > return NULL; > > @@ -836,8 +835,11 @@ msm_gpu_create_private_address_space(struct msm_gpu *gpu) > * If the target doesn't support private address spaces then return > * the global one > */ > - if (gpu->funcs->create_private_address_space) > + if (gpu->funcs->create_private_address_space) { > aspace = gpu->funcs->create_private_address_space(gpu); > + if (!IS_ERR(aspace)) > + aspace->pid = get_pid(task_pid(task)); > + } > > if (IS_ERR_OR_NULL(aspace)) > aspace = msm_gem_address_space_get(gpu->aspace); > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 4052a18e18c2..59f26bd0fe42 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -298,7 +298,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, > const char *name, struct msm_gpu_config *config); > > struct msm_gem_address_space * > -msm_gpu_create_private_address_space(struct msm_gpu *gpu); > +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task); > > void msm_gpu_cleanup(struct msm_gpu *gpu); > > -- > 2.26.2 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > Currently it doesn't matter, since we free the ctx immediately. But > when we start refcnt'ing the ctx, we don't want old dangling list > entries to hang around. > > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > index a1d94be7883a..90c9d84e6155 100644 > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) > * No lock needed in close and there won't > * be any more user ioctls coming our way > */ > - list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) > + list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) { > + list_del(&entry->node); If you refcount ctx, what does that do for the entries in the submit queue? "entry" here is kref'ed, but you're popping it off the list regardless of the put ends up freeing the object or not - which afaict would mean leaking the object. On the other hand, with the current implementation an object with higher refcount with adjacent objects of single refcount would end up with dangling pointers after the put. So in itself this change seems like a net gain, but I'm wondering about the plan described in the commit message. Regards, Bjorn > msm_submitqueue_put(entry); > + } > } > > int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, > -- > 2.26.2 >
On Thu 13 Aug 21:40 CDT 2020, Rob Clark wrote: > From: Jordan Crouse <jcrouse@codeaurora.org> > > Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected > by the io-pgtable configuration. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 ++++++++++++++++----- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 25 +++++++++++++++++++------ > 2 files changed, 35 insertions(+), 11 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index 37d8d49299b4..976d43a7f2ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -552,11 +552,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; > cb->ttbr[1] = 0; > } else { > - cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > - cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, > - cfg->asid); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > + cfg->asid); > cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > - cfg->asid); > + cfg->asid); The old indentation seems more appropriate. Apart from that this looks sensible. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > + > + if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) > + cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + else > + cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > } > } else { > cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; > @@ -822,7 +826,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, > > /* Update the domain's page sizes to reflect the page table format */ > domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; > - domain->geometry.aperture_end = (1UL << ias) - 1; > + > + if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { > + domain->geometry.aperture_start = ~0UL << ias; > + domain->geometry.aperture_end = ~0UL; > + } else { > + domain->geometry.aperture_end = (1UL << ias) - 1; > + } > + > domain->geometry.force_aperture = true; > > /* Initialise the context bank with our page table cfg */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 83294516ac08..f3e456893f28 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -169,10 +169,12 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_TCR 0x30 > #define ARM_SMMU_TCR_EAE BIT(31) > #define ARM_SMMU_TCR_EPD1 BIT(23) > +#define ARM_SMMU_TCR_A1 BIT(22) > #define ARM_SMMU_TCR_TG0 GENMASK(15, 14) > #define ARM_SMMU_TCR_SH0 GENMASK(13, 12) > #define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10) > #define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8) > +#define ARM_SMMU_TCR_EPD0 BIT(7) > #define ARM_SMMU_TCR_T0SZ GENMASK(5, 0) > > #define ARM_SMMU_VTCR_RES1 BIT(31) > @@ -350,12 +352,23 @@ struct arm_smmu_domain { > > static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) > { > - return ARM_SMMU_TCR_EPD1 | > - FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | > - FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | > - FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | > - FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | > - FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); > + u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | > + FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | > + FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | > + FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | > + FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); > + > + /* > + * When TTBR1 is selected shift the TCR fields by 16 bits and disable > + * translation in TTBR0 > + */ > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { > + tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1; > + tcr |= ARM_SMMU_TCR_EPD0; > + } else > + tcr |= ARM_SMMU_TCR_EPD1; > + > + return tcr; > } > > static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg) > -- > 2.26.2 >
On Mon, Aug 31, 2020 at 7:35 PM Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote: > > > From: Rob Clark <robdclark@chromium.org> > > > > Currently it doesn't matter, since we free the ctx immediately. But > > when we start refcnt'ing the ctx, we don't want old dangling list > > entries to hang around. > > > > Signed-off-by: Rob Clark <robdclark@chromium.org> > > --- > > drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > > index a1d94be7883a..90c9d84e6155 100644 > > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > > @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) > > * No lock needed in close and there won't > > * be any more user ioctls coming our way > > */ > > - list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) > > + list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) { > > + list_del(&entry->node); > > If you refcount ctx, what does that do for the entries in the submit > queue? > > "entry" here is kref'ed, but you're popping it off the list regardless > of the put ends up freeing the object or not - which afaict would mean > leaking the object. > What ends up happening is the submit has reference to submit-queue, which has reference to the ctx.. the submitqueue could be alive still pending in-flight submits (in a later patch), but dead from the PoV of userspace interface. We aren't relying (or at least aren't in the end, and I *think* I didn't miss anything in the middle) relying on ctx->submitqueues list to clean anything up in the end, just track what is still a valid submitqueue from userspace PoV BR, -R > > On the other hand, with the current implementation an object with higher > refcount with adjacent objects of single refcount would end up with > dangling pointers after the put. So in itself this change seems like a > net gain, but I'm wondering about the plan described in the commit > message. > > Regards, > Bjorn > > > msm_submitqueue_put(entry); > > + } > > } > > > > int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, > > -- > > 2.26.2 > >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > > Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include <linux/io-pgtable.h> > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > This will be populated by adreno-smmu, to provide a way for coordinating > enabling/disabling TTBR0 translation. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/adreno/adreno_device.c | 2 -- > drivers/gpu/drm/msm/msm_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_gpu.h | 6 +++++- > 3 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 26664e1b30c0..58e03b20e1c7 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -417,8 +417,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > return PTR_ERR(gpu); > } > > - dev_set_drvdata(dev, gpu); > - > return 0; > } > > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 6aa9e04e52e7..806eb0957280 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -892,7 +892,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, > gpu->gpu_cx = NULL; > > gpu->pdev = pdev; > - platform_set_drvdata(pdev, gpu); > + platform_set_drvdata(pdev, &gpu->adreno_smmu); > > msm_devfreq_init(gpu); > > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 8bda7beaed4b..f91b141add75 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -7,6 +7,7 @@ > #ifndef __MSM_GPU_H__ > #define __MSM_GPU_H__ > > +#include <linux/adreno-smmu-priv.h> > #include <linux/clk.h> > #include <linux/interconnect.h> > #include <linux/pm_opp.h> > @@ -73,6 +74,8 @@ struct msm_gpu { > struct platform_device *pdev; > const struct msm_gpu_funcs *funcs; > > + struct adreno_smmu_priv adreno_smmu; > + > /* performance counters (hw & sw): */ > spinlock_t perf_lock; > bool perfcntr_active; > @@ -143,7 +146,8 @@ struct msm_gpu { > > static inline struct msm_gpu *dev_to_gpu(struct device *dev) > { > - return dev_get_drvdata(dev); > + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev); > + return container_of(adreno_smmu, struct msm_gpu, adreno_smmu); > } > > /* It turns out that all targets use the same ringbuffer size */ > -- > 2.26.2 >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse <jcrouse@codeaurora.org> > > Add a special implementation for the SMMU attached to most Adreno GPU > target triggered from the qcom,adreno-smmu compatible string. > > The new Adreno SMMU implementation will enable split pagetables > (TTBR1) for the domain attached to the GPU device (SID 0) and > hard code it context bank 0 so the GPU hardware can implement > per-instance pagetables. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Co-developed-by: Rob Clark <robdclark@chromium.org> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 3 files changed, 151 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > index 88f17cc33023..d199b4bff15d 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > of_device_is_compatible(np, "qcom,sm8250-smmu-500")) > return qcom_smmu_impl_init(smmu); > > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) > + return qcom_adreno_smmu_impl_init(smmu); > + > if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) > smmu->impl = &mrvl_mmu500_impl; > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index be4318044f96..5640d9960610 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2019, The Linux Foundation. All rights reserved. > */ > > +#include <linux/adreno-smmu-priv.h> > #include <linux/of_device.h> > #include <linux/qcom_scm.h> > > @@ -12,6 +13,132 @@ struct qcom_smmu { > struct arm_smmu_device smmu; > }; > > +#define QCOM_ADRENO_SMMU_GPU_SID 0 > + > +static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > +{ > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > + int i; > + > + /* > + * The GPU will always use SID 0 so that is a handy way to uniquely > + * identify it and configure it for per-instance pagetables > + */ > + for (i = 0; i < fwspec->num_ids; i++) { > + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); > + > + if (sid == QCOM_ADRENO_SMMU_GPU_SID) > + return true; > + } > + > + return false; > +} > + > +static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( > + const void *cookie) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = > + io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + return &pgtable->cfg; > +} > + > +/* > + * Local implementation to configure TTBR0 with the specified pagetable config. > + * The GPU driver will call this to enable TTBR0 when per-instance pagetables > + * are active > + */ > + > +static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, > + const struct io_pgtable_cfg *pgtbl_cfg) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; > + > + /* The domain must have split pagetables already enabled */ > + if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) > + return -EINVAL; > + > + /* If the pagetable config is NULL, disable TTBR0 */ > + if (!pgtbl_cfg) { > + /* Do nothing if it is already disabled */ > + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + /* Set TCR to the original configuration */ > + cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } else { > + u32 tcr = cb->tcr[0]; > + > + /* Don't call this again if TTBR0 is already enabled */ > + if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); > + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); > + > + cb->tcr[0] = tcr; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } > + > + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); > + > + return 0; > +} > + > +static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, > + struct device *dev, int start, int count) > +{ > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + /* > + * Assign context bank 0 to the GPU device so the GPU hardware can > + * switch pagetables > + */ > + if (qcom_adreno_smmu_is_gpu_device(dev)) { > + start = 0; > + count = 1; > + } else { > + start = 1; > + } > + > + return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > +} > + > +static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > +{ > + struct adreno_smmu_priv *priv; > + > + /* Only enable split pagetables for the GPU device (SID 0) */ > + if (!qcom_adreno_smmu_is_gpu_device(dev)) > + return 0; > + > + /* > + * All targets that use the qcom,adreno-smmu compatible string *should* > + * be AARCH64 stage 1 but double check because the arm-smmu code assumes > + * that is the case when the TTBR1 quirk is enabled > + */ > + if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > + pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > + > + /* > + * Initialize private interface with GPU: > + */ > + > + priv = dev_get_drvdata(dev); > + priv->cookie = smmu_domain; > + priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > + priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + > + return 0; > +} > + > static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { > { .compatible = "qcom,adreno" }, > { .compatible = "qcom,mdp4" }, > @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { > .reset = qcom_smmu500_reset, > }; > > -struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +static const struct arm_smmu_impl qcom_adreno_smmu_impl = { > + .init_context = qcom_adreno_smmu_init_context, > + .def_domain_type = qcom_smmu_def_domain_type, > + .reset = qcom_smmu500_reset, > + .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, > +}; > + > +static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, > + const struct arm_smmu_impl *impl) > { > struct qcom_smmu *qsmmu; > > @@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > > qsmmu->smmu = *smmu; > > - qsmmu->smmu.impl = &qcom_smmu_impl; > + qsmmu->smmu.impl = impl; > devm_kfree(smmu->dev, smmu); > > return &qsmmu->smmu; > } > + > +struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > +} > + > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > +} > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 27c83333fc50..cd75a33967bb 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu); > > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); > int arm_mmu500_reset(struct arm_smmu_device *smmu); > -- > 2.26.2 >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse <jcrouse@codeaurora.org> > > Each submitqueue is attached to a context. Add a pointer to the > context to the submitqueue at create time and refcount it so > that it stays around through the life of the queue. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Co-developed-by: Rob Clark <robdclark@chromium.org> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_drv.c | 3 ++- > drivers/gpu/drm/msm/msm_drv.h | 20 ++++++++++++++++++++ > drivers/gpu/drm/msm/msm_gem.h | 1 + > drivers/gpu/drm/msm/msm_gem_submit.c | 6 +++--- > drivers/gpu/drm/msm/msm_gpu.h | 1 + > drivers/gpu/drm/msm/msm_submitqueue.c | 3 +++ > 6 files changed, 30 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c > index 7d641c7e3514..01845a3b8d52 100644 > --- a/drivers/gpu/drm/msm/msm_drv.c > +++ b/drivers/gpu/drm/msm/msm_drv.c > @@ -594,6 +594,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) > if (!ctx) > return -ENOMEM; > > + kref_init(&ctx->ref); > msm_submitqueue_init(dev, ctx); > > ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL; > @@ -615,7 +616,7 @@ static int msm_open(struct drm_device *dev, struct drm_file *file) > static void context_close(struct msm_file_private *ctx) > { > msm_submitqueue_close(ctx); > - kfree(ctx); > + msm_file_private_put(ctx); > } > > static void msm_postclose(struct drm_device *dev, struct drm_file *file) > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index af259b0573ea..4561bfb5e745 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -57,6 +57,7 @@ struct msm_file_private { > struct list_head submitqueues; > int queueid; > struct msm_gem_address_space *aspace; > + struct kref ref; > }; > > enum msm_mdp_plane_property { > @@ -428,6 +429,25 @@ void msm_submitqueue_close(struct msm_file_private *ctx); > > void msm_submitqueue_destroy(struct kref *kref); > > +static inline void __msm_file_private_destroy(struct kref *kref) > +{ > + struct msm_file_private *ctx = container_of(kref, > + struct msm_file_private, ref); > + > + kfree(ctx); > +} > + > +static inline void msm_file_private_put(struct msm_file_private *ctx) > +{ > + kref_put(&ctx->ref, __msm_file_private_destroy); > +} > + > +static inline struct msm_file_private *msm_file_private_get( > + struct msm_file_private *ctx) > +{ > + kref_get(&ctx->ref); > + return ctx; > +} > > #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) > #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) > diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h > index 972490b14ba5..9c573c4269cb 100644 > --- a/drivers/gpu/drm/msm/msm_gem.h > +++ b/drivers/gpu/drm/msm/msm_gem.h > @@ -142,6 +142,7 @@ struct msm_gem_submit { > bool valid; /* true if no cmdstream patching needed */ > bool in_rb; /* "sudo" mode, copy cmds into RB */ > struct msm_ringbuffer *ring; > + struct msm_file_private *ctx; > unsigned int nr_cmds; > unsigned int nr_bos; > u32 ident; /* A "identifier" for the submit for logging */ > diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c > index 8cb9aa15ff90..1464b04d25d3 100644 > --- a/drivers/gpu/drm/msm/msm_gem_submit.c > +++ b/drivers/gpu/drm/msm/msm_gem_submit.c > @@ -27,7 +27,7 @@ > #define BO_PINNED 0x2000 > > static struct msm_gem_submit *submit_create(struct drm_device *dev, > - struct msm_gpu *gpu, struct msm_gem_address_space *aspace, > + struct msm_gpu *gpu, > struct msm_gpu_submitqueue *queue, uint32_t nr_bos, > uint32_t nr_cmds) > { > @@ -43,7 +43,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, > return NULL; > > submit->dev = dev; > - submit->aspace = aspace; > + submit->aspace = queue->ctx->aspace; > submit->gpu = gpu; > submit->fence = NULL; > submit->cmd = (void *)&submit->bos[nr_bos]; > @@ -677,7 +677,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, > } > } > > - submit = submit_create(dev, gpu, ctx->aspace, queue, args->nr_bos, > + submit = submit_create(dev, gpu, queue, args->nr_bos, > args->nr_cmds); > if (!submit) { > ret = -ENOMEM; > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index f91b141add75..97c527e98391 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -190,6 +190,7 @@ struct msm_gpu_submitqueue { > u32 flags; > u32 prio; > int faults; > + struct msm_file_private *ctx; > struct list_head node; > struct kref ref; > }; > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > index 90c9d84e6155..c3d206105d28 100644 > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > @@ -12,6 +12,8 @@ void msm_submitqueue_destroy(struct kref *kref) > struct msm_gpu_submitqueue *queue = container_of(kref, > struct msm_gpu_submitqueue, ref); > > + msm_file_private_put(queue->ctx); > + > kfree(queue); > } > > @@ -83,6 +85,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, > > write_lock(&ctx->queuelock); > > + queue->ctx = msm_file_private_get(ctx); > queue->id = ctx->queueid++; > > if (id) > -- > 2.26.2 >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse <jcrouse@codeaurora.org> > > Use the aperture settings from the IOMMU domain to set up the virtual > address range for the GPU. This allows us to transparently deal with > IOMMU side features (like split pagetables). > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++++++++-- > drivers/gpu/drm/msm/msm_iommu.c | 7 +++++++ > 2 files changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 533a34b4cce2..34e6242c1767 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -192,9 +192,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, > struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type); > struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu); > struct msm_gem_address_space *aspace; > + u64 start, size; > > - aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M, > - 0xffffffff - SZ_16M); > + /* > + * Use the aperture start or SZ_16M, whichever is greater. This will > + * ensure that we align with the allocated pagetable range while still > + * allowing room in the lower 32 bits for GMEM and whatnot > + */ > + start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); > + size = iommu->geometry.aperture_end - start + 1; > + > + aspace = msm_gem_address_space_create(mmu, "gpu", > + start & GENMASK(48, 0), size); > > if (IS_ERR(aspace) && !IS_ERR(mmu)) > mmu->funcs->destroy(mmu); > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > index 3a381a9674c9..1b6635504069 100644 > --- a/drivers/gpu/drm/msm/msm_iommu.c > +++ b/drivers/gpu/drm/msm/msm_iommu.c > @@ -36,6 +36,10 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, > struct msm_iommu *iommu = to_msm_iommu(mmu); > size_t ret; > > + /* The arm-smmu driver expects the addresses to be sign extended */ > + if (iova & BIT_ULL(48)) > + iova |= GENMASK_ULL(63, 49); > + > ret = iommu_map_sg(iommu->domain, iova, sgt->sgl, sgt->nents, prot); > WARN_ON(!ret); > > @@ -46,6 +50,9 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) > { > struct msm_iommu *iommu = to_msm_iommu(mmu); > > + if (iova & BIT_ULL(48)) > + iova |= GENMASK_ULL(63, 49); > + > iommu_unmap(iommu->domain, iova, len); > > return 0; > -- > 2.26.2 >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse <jcrouse@codeaurora.org> > > Add support to create a io-pgtable for use by targets that support > per-instance pagetables. In order to support per-instance pagetables the > GPU SMMU device needs to have the qcom,adreno-smmu compatible string and > split pagetables enabled. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_gpummu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 199 ++++++++++++++++++++++++++++++- > drivers/gpu/drm/msm/msm_mmu.h | 16 ++- > 3 files changed, 214 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/msm_gpummu.c > index 310a31b05faa..aab121f4beb7 100644 > --- a/drivers/gpu/drm/msm/msm_gpummu.c > +++ b/drivers/gpu/drm/msm/msm_gpummu.c > @@ -102,7 +102,7 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) > } > > gpummu->gpu = gpu; > - msm_mmu_init(&gpummu->base, dev, &funcs); > + msm_mmu_init(&gpummu->base, dev, &funcs, MSM_MMU_GPUMMU); > > return &gpummu->base; > } > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > index 1b6635504069..697cc0a059d6 100644 > --- a/drivers/gpu/drm/msm/msm_iommu.c > +++ b/drivers/gpu/drm/msm/msm_iommu.c > @@ -4,15 +4,210 @@ > * Author: Rob Clark <robdclark@gmail.com> > */ > > +#include <linux/adreno-smmu-priv.h> > +#include <linux/io-pgtable.h> > #include "msm_drv.h" > #include "msm_mmu.h" > > struct msm_iommu { > struct msm_mmu base; > struct iommu_domain *domain; > + atomic_t pagetables; > }; > + > #define to_msm_iommu(x) container_of(x, struct msm_iommu, base) > > +struct msm_iommu_pagetable { > + struct msm_mmu base; > + struct msm_mmu *parent; > + struct io_pgtable_ops *pgtbl_ops; > + phys_addr_t ttbr; > + u32 asid; > +}; > +static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu) > +{ > + return container_of(mmu, struct msm_iommu_pagetable, base); > +} > + > +static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, > + size_t size) > +{ > + struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); > + struct io_pgtable_ops *ops = pagetable->pgtbl_ops; > + size_t unmapped = 0; > + > + /* Unmap the block one page at a time */ > + while (size) { > + unmapped += ops->unmap(ops, iova, 4096, NULL); > + iova += 4096; > + size -= 4096; > + } > + > + iommu_flush_tlb_all(to_msm_iommu(pagetable->parent)->domain); > + > + return (unmapped == size) ? 0 : -EINVAL; > +} > + > +static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova, > + struct sg_table *sgt, size_t len, int prot) > +{ > + struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); > + struct io_pgtable_ops *ops = pagetable->pgtbl_ops; > + struct scatterlist *sg; > + size_t mapped = 0; > + u64 addr = iova; > + unsigned int i; > + > + for_each_sg(sgt->sgl, sg, sgt->nents, i) { > + size_t size = sg->length; > + phys_addr_t phys = sg_phys(sg); > + > + /* Map the block one page at a time */ > + while (size) { > + if (ops->map(ops, addr, phys, 4096, prot, GFP_KERNEL)) { > + msm_iommu_pagetable_unmap(mmu, iova, mapped); > + return -EINVAL; > + } > + > + phys += 4096; > + addr += 4096; > + size -= 4096; > + mapped += 4096; > + } > + } > + > + return 0; > +} > + > +static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu) > +{ > + struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); > + struct msm_iommu *iommu = to_msm_iommu(pagetable->parent); > + struct adreno_smmu_priv *adreno_smmu = > + dev_get_drvdata(pagetable->parent->dev); > + > + /* > + * If this is the last attached pagetable for the parent, > + * disable TTBR0 in the arm-smmu driver > + */ > + if (atomic_dec_return(&iommu->pagetables) == 0) > + adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL); > + > + free_io_pgtable_ops(pagetable->pgtbl_ops); > + kfree(pagetable); > +} > + > +int msm_iommu_pagetable_params(struct msm_mmu *mmu, > + phys_addr_t *ttbr, int *asid) > +{ > + struct msm_iommu_pagetable *pagetable; > + > + if (mmu->type != MSM_MMU_IOMMU_PAGETABLE) > + return -EINVAL; > + > + pagetable = to_pagetable(mmu); > + > + if (ttbr) > + *ttbr = pagetable->ttbr; > + > + if (asid) > + *asid = pagetable->asid; > + > + return 0; > +} > + > +static const struct msm_mmu_funcs pagetable_funcs = { > + .map = msm_iommu_pagetable_map, > + .unmap = msm_iommu_pagetable_unmap, > + .destroy = msm_iommu_pagetable_destroy, > +}; > + > +static void msm_iommu_tlb_flush_all(void *cookie) > +{ > +} > + > +static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size, > + size_t granule, void *cookie) > +{ > +} > + > +static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather, > + unsigned long iova, size_t granule, void *cookie) > +{ > +} > + > +static const struct iommu_flush_ops null_tlb_ops = { > + .tlb_flush_all = msm_iommu_tlb_flush_all, > + .tlb_flush_walk = msm_iommu_tlb_flush_walk, > + .tlb_flush_leaf = msm_iommu_tlb_flush_walk, > + .tlb_add_page = msm_iommu_tlb_add_page, > +}; > + > +struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) > +{ > + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); > + struct msm_iommu *iommu = to_msm_iommu(parent); > + struct msm_iommu_pagetable *pagetable; > + const struct io_pgtable_cfg *ttbr1_cfg = NULL; > + struct io_pgtable_cfg ttbr0_cfg; > + int ret; > + > + /* Get the pagetable configuration from the domain */ > + if (adreno_smmu->cookie) > + ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); > + if (!ttbr1_cfg) > + return ERR_PTR(-ENODEV); > + > + pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); > + if (!pagetable) > + return ERR_PTR(-ENOMEM); > + > + msm_mmu_init(&pagetable->base, parent->dev, &pagetable_funcs, > + MSM_MMU_IOMMU_PAGETABLE); > + > + /* Clone the TTBR1 cfg as starting point for TTBR0 cfg: */ > + ttbr0_cfg = *ttbr1_cfg; > + > + /* The incoming cfg will have the TTBR1 quirk enabled */ > + ttbr0_cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1; > + ttbr0_cfg.tlb = &null_tlb_ops; > + > + pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1, > + &ttbr0_cfg, iommu->domain); > + > + if (!pagetable->pgtbl_ops) { > + kfree(pagetable); > + return ERR_PTR(-ENOMEM); > + } > + > + /* > + * If this is the first pagetable that we've allocated, send it back to > + * the arm-smmu driver as a trigger to set up TTBR0 > + */ > + if (atomic_inc_return(&iommu->pagetables) == 1) { > + ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg); > + if (ret) { > + free_io_pgtable_ops(pagetable->pgtbl_ops); > + kfree(pagetable); > + return ERR_PTR(ret); > + } > + } > + > + /* Needed later for TLB flush */ > + pagetable->parent = parent; > + pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; > + > + /* > + * TODO we would like each set of page tables to have a unique ASID > + * to optimize TLB invalidation. But iommu_flush_tlb_all() will > + * end up flushing the ASID used for TTBR1 pagetables, which is not > + * what we want. So for now just use the same ASID as TTBR1. > + */ > + pagetable->asid = 0; > + > + return &pagetable->base; > +} > + > static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, > unsigned long iova, int flags, void *arg) > { > @@ -85,9 +280,11 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) > return ERR_PTR(-ENOMEM); > > iommu->domain = domain; > - msm_mmu_init(&iommu->base, dev, &funcs); > + msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); > iommu_set_fault_handler(domain, msm_fault_handler, iommu); > > + atomic_set(&iommu->pagetables, 0); > + > ret = iommu_attach_device(iommu->domain, dev); > if (ret) { > kfree(iommu); > diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h > index 3a534ee59bf6..61ade89d9e48 100644 > --- a/drivers/gpu/drm/msm/msm_mmu.h > +++ b/drivers/gpu/drm/msm/msm_mmu.h > @@ -17,18 +17,26 @@ struct msm_mmu_funcs { > void (*destroy)(struct msm_mmu *mmu); > }; > > +enum msm_mmu_type { > + MSM_MMU_GPUMMU, > + MSM_MMU_IOMMU, > + MSM_MMU_IOMMU_PAGETABLE, > +}; > + > struct msm_mmu { > const struct msm_mmu_funcs *funcs; > struct device *dev; > int (*handler)(void *arg, unsigned long iova, int flags); > void *arg; > + enum msm_mmu_type type; > }; > > static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, > - const struct msm_mmu_funcs *funcs) > + const struct msm_mmu_funcs *funcs, enum msm_mmu_type type) > { > mmu->dev = dev; > mmu->funcs = funcs; > + mmu->type = type; > } > > struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); > @@ -41,7 +49,13 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, > mmu->handler = handler; > } > > +struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent); > + > void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, > dma_addr_t *tran_error); > > + > +int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, > + int *asid); > + > #endif /* __MSM_MMU_H__ */ > -- > 2.26.2 >
On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > In $debugfs/gem we already show any vma(s) associated with an object. > Also show process names if the vma's address space is a per-process > address space. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/msm_drv.c | 2 +- > drivers/gpu/drm/msm/msm_gem.c | 25 +++++++++++++++++++++---- > drivers/gpu/drm/msm/msm_gem.h | 5 +++++ > drivers/gpu/drm/msm/msm_gem_vma.c | 1 + > drivers/gpu/drm/msm/msm_gpu.c | 8 +++++--- > drivers/gpu/drm/msm/msm_gpu.h | 2 +- > 6 files changed, 34 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c > index 8e70d220bba8..8d5c4f98c332 100644 > --- a/drivers/gpu/drm/msm/msm_drv.c > +++ b/drivers/gpu/drm/msm/msm_drv.c > @@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) > kref_init(&ctx->ref); > msm_submitqueue_init(dev, ctx); > > - ctx->aspace = msm_gpu_create_private_address_space(priv->gpu); > + ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); > file->driver_priv = ctx; > > return 0; > diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c > index 3cb7aeb93fd3..76a6c5271e57 100644 > --- a/drivers/gpu/drm/msm/msm_gem.c > +++ b/drivers/gpu/drm/msm/msm_gem.c > @@ -842,11 +842,28 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m) > > seq_puts(m, " vmas:"); > > - list_for_each_entry(vma, &msm_obj->vmas, list) > - seq_printf(m, " [%s: %08llx,%s,inuse=%d]", > - vma->aspace != NULL ? vma->aspace->name : NULL, > - vma->iova, vma->mapped ? "mapped" : "unmapped", > + list_for_each_entry(vma, &msm_obj->vmas, list) { > + const char *name, *comm; > + if (vma->aspace) { > + struct msm_gem_address_space *aspace = vma->aspace; > + struct task_struct *task = > + get_pid_task(aspace->pid, PIDTYPE_PID); > + if (task) { > + comm = kstrdup(task->comm, GFP_KERNEL); > + } else { > + comm = NULL; > + } > + name = aspace->name; > + } else { > + name = comm = NULL; > + } > + seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s,inuse=%d]", > + name, comm ? ":" : "", comm ? comm : "", > + vma->aspace, vma->iova, > + vma->mapped ? "mapped" : "unmapped", > vma->inuse); > + kfree(comm); > + } > > seq_puts(m, "\n"); > } > diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h > index 9c573c4269cb..7b1c7a5f8eef 100644 > --- a/drivers/gpu/drm/msm/msm_gem.h > +++ b/drivers/gpu/drm/msm/msm_gem.h > @@ -24,6 +24,11 @@ struct msm_gem_address_space { > spinlock_t lock; /* Protects drm_mm node allocation/removal */ > struct msm_mmu *mmu; > struct kref kref; > + > + /* For address spaces associated with a specific process, this > + * will be non-NULL: > + */ > + struct pid *pid; > }; > > struct msm_gem_vma { > diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c > index 29cc1305cf37..80a8a266d68f 100644 > --- a/drivers/gpu/drm/msm/msm_gem_vma.c > +++ b/drivers/gpu/drm/msm/msm_gem_vma.c > @@ -17,6 +17,7 @@ msm_gem_address_space_destroy(struct kref *kref) > drm_mm_takedown(&aspace->mm); > if (aspace->mmu) > aspace->mmu->funcs->destroy(aspace->mmu); > + put_pid(aspace->pid); > kfree(aspace); > } > > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 951850804d77..ac8961187a73 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -825,10 +825,9 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) > > /* Return a new address space for a msm_drm_private instance */ > struct msm_gem_address_space * > -msm_gpu_create_private_address_space(struct msm_gpu *gpu) > +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) > { > struct msm_gem_address_space *aspace = NULL; > - > if (!gpu) > return NULL; > > @@ -836,8 +835,11 @@ msm_gpu_create_private_address_space(struct msm_gpu *gpu) > * If the target doesn't support private address spaces then return > * the global one > */ > - if (gpu->funcs->create_private_address_space) > + if (gpu->funcs->create_private_address_space) { > aspace = gpu->funcs->create_private_address_space(gpu); > + if (!IS_ERR(aspace)) > + aspace->pid = get_pid(task_pid(task)); > + } > > if (IS_ERR_OR_NULL(aspace)) > aspace = msm_gem_address_space_get(gpu->aspace); > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 4052a18e18c2..59f26bd0fe42 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -298,7 +298,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, > const char *name, struct msm_gpu_config *config); > > struct msm_gem_address_space * > -msm_gpu_create_private_address_space(struct msm_gpu *gpu); > +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task); > > void msm_gpu_cleanup(struct msm_gpu *gpu); > > -- > 2.26.2 >
On Tue 01 Sep 03:42 UTC 2020, Rob Clark wrote: > On Mon, Aug 31, 2020 at 7:35 PM Bjorn Andersson > <bjorn.andersson@linaro.org> wrote: > > > > On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote: > > > > > From: Rob Clark <robdclark@chromium.org> > > > > > > Currently it doesn't matter, since we free the ctx immediately. But > > > when we start refcnt'ing the ctx, we don't want old dangling list > > > entries to hang around. > > > > > > Signed-off-by: Rob Clark <robdclark@chromium.org> > > > --- > > > drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > > > index a1d94be7883a..90c9d84e6155 100644 > > > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > > > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > > > @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) > > > * No lock needed in close and there won't > > > * be any more user ioctls coming our way > > > */ > > > - list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) > > > + list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) { > > > + list_del(&entry->node); > > > > If you refcount ctx, what does that do for the entries in the submit > > queue? > > > > "entry" here is kref'ed, but you're popping it off the list regardless > > of the put ends up freeing the object or not - which afaict would mean > > leaking the object. > > > > What ends up happening is the submit has reference to submit-queue, > which has reference to the ctx.. the submitqueue could be alive still > pending in-flight submits (in a later patch), but dead from the PoV of > userspace interface. > > We aren't relying (or at least aren't in the end, and I *think* I > didn't miss anything in the middle) relying on ctx->submitqueues list > to clean anything up in the end, just track what is still a valid > submitqueue from userspace PoV > Looks reasonable, thanks for the explanation. > BR, > -R > > > > > On the other hand, with the current implementation an object with higher > > refcount with adjacent objects of single refcount would end up with > > dangling pointers after the put. So in itself this change seems like a > > net gain, but I'm wondering about the plan described in the commit > > message. > > > > Regards, > > Bjorn > > > > > msm_submitqueue_put(entry); > > > + } > > > } > > > > > > int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, > > > -- > > > 2.26.2 > > >
On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > Currently it doesn't matter, since we free the ctx immediately. But > when we start refcnt'ing the ctx, we don't want old dangling list > entries to hang around. > > Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c > index a1d94be7883a..90c9d84e6155 100644 > --- a/drivers/gpu/drm/msm/msm_submitqueue.c > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c > @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) > * No lock needed in close and there won't > * be any more user ioctls coming our way > */ > - list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) > + list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) { > + list_del(&entry->node); > msm_submitqueue_put(entry); > + } > } > > int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, > -- > 2.26.2 >
This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware pagetable switching. The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during runtime to allow each individual instance or application to have its own pagetable. In order to take advantage of the HW capabilities there are certain requirements needed of the SMMU hardware. This series adds support for an Adreno specific arm-smmu implementation. The new implementation 1) ensures that the GPU domain is always assigned context bank 0, 2) enables split pagetable support (TTBR1) so that the instance specific pagetable can be swapped while the global memory remains in place and 3) shares the current pagetable configuration with the GPU driver to allow it to create its own io-pgtable instances. The series then adds the drm/msm code to enable these features. For targets that support it allocate new pagetables using the io-pgtable configuration shared by the arm-smmu driver and swap them in during runtime. This version of the series merges the previous patchset(s) [1] and [2] with the following improvements: v12: - Nitpick cleanups in gpu/drm/msm/msm_iommu.c (Rob Clark) - Reorg in gpu/drm/msm/msm_gpu.c (Rob Clark) - Use the default asid for the context bank so that iommu_tlb_flush_all works - Flush the UCHE after a page switch - Add the SCTLR.HUPCF patch at the end of the series v11: - Add implementation specific get_attr/set_attr functions (per Rob Clark) - Fix context bank allocation (per Bjorn Andersson) v10: - arm-smmu: add implementation hook to allocate context banks - arm-smmu: Match the GPU domain by stream ID instead of compatible string - arm-smmu: Make DOMAIN_ATTR_PGTABLE_CFG bi-directional. The leaf driver queries the configuration to create a pagetable and then sends the newly created configuration back to the smmu-driver to enable TTBR0 - drm/msm: Add context reference counting for submissions - drm/msm: Use dummy functions to skip TLB operations on per-instance pagetables [1] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045653.html [2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html Jordan Crouse (13): iommu/arm-smmu: Pass io-pgtable config to implementation specific function iommu/arm-smmu: Add support for split pagetables iommu/arm-smmu: Prepare for the adreno-smmu implementation iommu: Add a domain attribute to get/set a pagetable configuration iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU drm/msm: Add a context pointer to the submitqueue drm/msm: Set the global virtual address range from the IOMMU domain drm/msm: Add support to create a local pagetable drm/msm: Add support for private address space instances drm/msm/a6xx: Add support for per-instance pagetables arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU iommu/arm-smmu: Add a init_context_bank implementation hook .../devicetree/bindings/iommu/arm,smmu.yaml | 4 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 75 ++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +- drivers/gpu/drm/msm/msm_drv.c | 16 +- drivers/gpu/drm/msm/msm_drv.h | 13 ++ drivers/gpu/drm/msm/msm_gem.h | 1 + drivers/gpu/drm/msm/msm_gem_submit.c | 8 +- drivers/gpu/drm/msm/msm_gem_vma.c | 9 + drivers/gpu/drm/msm/msm_gpu.c | 31 ++- drivers/gpu/drm/msm/msm_gpu.h | 12 +- drivers/gpu/drm/msm/msm_gpummu.c | 2 +- drivers/gpu/drm/msm/msm_iommu.c | 197 +++++++++++++++++- drivers/gpu/drm/msm/msm_mmu.h | 16 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + drivers/gpu/drm/msm/msm_submitqueue.c | 8 +- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 6 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 172 ++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 134 ++++++------ drivers/iommu/arm/arm-smmu/arm-smmu.h | 87 +++++++- include/linux/iommu.h | 1 + 24 files changed, 708 insertions(+), 121 deletions(-)