| Message ID | 20210210133458.1201066-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS | expand |
Colleagues, On Wed, 10 Feb 2021 at 16:36, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > GENI SPI controller shows several issues if it manages the CS on its own > (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to > use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. Should I improve this patchset in any way or is it fine to go? > Changes since v3: > - Rephrase qrb5165-rb5 commit > - Remove leftover pinctrl-name entries for spi0 > - Group pinctrl entries at the end of qrb5165-rb5. > > Changes since v2: > - Move pinctrl-names to the board file. > - Reorder CS/CS-gpio/data-clk nodes to follow alphabetical sort. > > Changes since v1: > - Split sm8250's spi pin config into mux/config parts, split away CS > handling from main SPI pinctrl nodes. > > ---------------------------------------------------------------- > Dmitry Baryshkov (4): > arm64: dts: qcom: sm8250: split spi pinctrl config > arm64: dts: qcom: sm8250: further split of spi pinctrl config > arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS > arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS > > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 14 + > arch/arm64/boot/dts/qcom/sm8250.dtsi | 540 +++++++++++++++---------------- > 2 files changed, 274 insertions(+), 280 deletions(-) > > -- With best wishes Dmitry
Hello: This series was applied to qcom/linux.git (refs/heads/for-next): On Wed, 10 Feb 2021 16:34:54 +0300 you wrote: > GENI SPI controller shows several issues if it manages the CS on its own > (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to > use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. > > Changes since v3: > - Rephrase qrb5165-rb5 commit > - Remove leftover pinctrl-name entries for spi0 > - Group pinctrl entries at the end of qrb5165-rb5. > > [...] Here is the summary with links: - [v4,1/4] arm64: dts: qcom: sm8250: split spi pinctrl config https://git.kernel.org/qcom/c/d3769729dbad - [v4,2/4] arm64: dts: qcom: sm8250: further split of spi pinctrl config https://git.kernel.org/qcom/c/c88f9ecc0ef3 - [v4,3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS https://git.kernel.org/qcom/c/eb97ccbba0fe - [v4,4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS https://git.kernel.org/qcom/c/e9269650db2f You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. Changes since v3: - Rephrase qrb5165-rb5 commit - Remove leftover pinctrl-name entries for spi0 - Group pinctrl entries at the end of qrb5165-rb5. Changes since v2: - Move pinctrl-names to the board file. - Reorder CS/CS-gpio/data-clk nodes to follow alphabetical sort. Changes since v1: - Split sm8250's spi pin config into mux/config parts, split away CS handling from main SPI pinctrl nodes. ---------------------------------------------------------------- Dmitry Baryshkov (4): arm64: dts: qcom: sm8250: split spi pinctrl config arm64: dts: qcom: sm8250: further split of spi pinctrl config arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 14 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 540 +++++++++++++++---------------- 2 files changed, 274 insertions(+), 280 deletions(-)