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[00/13] arm64: dts: qcom: Update sc7180-trogdor variants from downstream

Message ID 20210225221310.1939599-1-dianders@chromium.org
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Series arm64: dts: qcom: Update sc7180-trogdor variants from downstream | expand

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Doug Anderson Feb. 25, 2021, 10:12 p.m. UTC
The point of this series is to catch upstream up to what we have
downstream in terms of sc7180-trogdor variants.  Notably:
- It incorporates minor changes that snuck into the trogdor and lazor
  device tree files since they were posted upstream.
- It adds the "Limozeen" SKU variant of Lazor.
- It adds support the Pompom and CoachZ type trogdor boards.

This series was tested on mainline Linux instead of the Qualcomm tree
since mainline has important bugfixes that are not in the current
Qualcomm tree. Given the current state of the merge window mainline
has all of the relevant Qualcomm device tree files anyway. For
testing, I picked these atop mainline:
- Commit fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
  to keep the GPU from crashing due to the fact that commit
  20fd3b37285b ("arm64: dts: qcom: sc7180: Add support for gpu fuse")
  is in mainline.  This commit is in msm-next.
- The patch ("arm64: dts: qcom: sc7180: Use pdc interrupts for USB
  instead of GIC interrupts") [1] just because it reduced diffs and
  seemed ready to go.
- The patch ("arm64: dts: qcom: sc7180: Avoid glitching SPI CS at
  bootup on trogdor") [2] because that's an important bugfix.

With all these changes things are in pretty good shape. Looking at
diffs compared to downstream w/ a few patches [3]:
- I haven't tried to resolve "sound" with upstream, instead stripping
  / leaving as-is any audio related nodes.  Someone with more
  knowledge of the current state of audio needs to take a pass here.
- I haven't tried to resolve DP with upstream.  It's basically not
  there.  Someone who works on this: please help!
- We have a downstream patch to manage power for USB hubs.  Without
  that we have to keep power on all the time for USB.  Matthias is
  still working on trying to get an agreement for how that should
  work.
- Downstream we have an early version of the "sleep stats" driver
  landed.  I believe this is in Maulik's court to re-post.

I have tested this series on "lazor", "lazor-limozeen", "pompom" and
"coachz".  All of them boot to the web browser with this patch series.

I have confirmed that Matthias's recent charger series [4] applies
atop this with no conflicts, though I haven't looked at exactly which
revs of coachz / pompom need a similar change.  It might be easiest to
just follow up once both series land and we get final confirmation
about exactly which revs will have exactly which thermistor.

[1] https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.org
[2] https://lore.kernel.org/r/20210218145456.1.I1da01a075dd86e005152f993b2d5d82dd9686238@changeid
[3] https://chromium.googlesource.com/chromiumos/third_party/kernel/+log/refs/sandbox/dianders/210225-downstream-dts
[4] https://lore.kernel.org/linux-arm-msm/20210225103330.v2.1.I6a426324db3d98d6cfae8adf2598831bb30bba74@changeid/


Abhishek Kumar (1):
  arm64: dts: qcom: sc7180: add GO_LAZOR variant property for lazor

Alexandru M Stan (1):
  arm64: dts: qcom: sc7180-trogdor: Remove fp control pins in prep for
    coachz

Douglas Anderson (6):
  arm64: dts: qcom: Move sc7180 MI2S config to board files and make
    pulldown
  arm64: dts: qcom: Prep sc7180-trogdor trackpad IRQ for new boards
  arm64: dts: qcom: Unify the sc7180-trogdor panel nodes
  arm64: dts: qcom: Add sc7180-lazor-limozeen skus
  arm64: dts: qcom: Add sc7180-lazor-pompom skus
  arm64: dts: qcom: Add sc7180-lazor-coachz skus

Matthias Kaehlcke (1):
  arm64: dts: qcom: sc7180: Set up lazor r3+ as sc7180-lite SKUs

Stephen Boyd (3):
  arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy
  arm64: dts: qcom: trogdor: Only wakeup from pen eject
  arm64: dts: qcom: Disable camera clk on sc7180-trogdor devices by
    default

Venkata Lakshmi Narayana Gubba (1):
  arm64: dts: qcom: sc7180: Remove clock for bluetooth on Trogdor

 arch/arm64/boot/dts/qcom/Makefile             |  11 +
 .../dts/qcom/sc7180-trogdor-coachz-r1-lte.dts |  18 ++
 .../dts/qcom/sc7180-trogdor-coachz-r1.dts     | 154 ++++++++++
 .../dts/qcom/sc7180-trogdor-coachz-r2-lte.dts |  18 ++
 .../dts/qcom/sc7180-trogdor-coachz-r2.dts     |  15 +
 .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi  | 249 +++++++++++++++
 .../sc7180-trogdor-lazor-limozeen-nots-r4.dts |  34 +++
 .../sc7180-trogdor-lazor-limozeen-nots.dts    |  26 ++
 .../qcom/sc7180-trogdor-lazor-limozeen.dts    |  42 +++
 .../dts/qcom/sc7180-trogdor-lazor-r3-kb.dts   |   5 +-
 .../dts/qcom/sc7180-trogdor-lazor-r3-lte.dts  |   4 +-
 .../boot/dts/qcom/sc7180-trogdor-lazor-r3.dts |   1 +
 .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi   |  39 +--
 .../dts/qcom/sc7180-trogdor-pompom-r1-lte.dts |  14 +
 .../dts/qcom/sc7180-trogdor-pompom-r1.dts     |  26 ++
 .../dts/qcom/sc7180-trogdor-pompom-r2-lte.dts |  14 +
 .../dts/qcom/sc7180-trogdor-pompom-r2.dts     |  44 +++
 .../boot/dts/qcom/sc7180-trogdor-pompom.dtsi  | 288 ++++++++++++++++++
 .../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts |  35 ++-
 arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi  | 105 +++----
 arch/arm64/boot/dts/qcom/sc7180.dtsi          |  41 +--
 21 files changed, 1073 insertions(+), 110 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi

Comments

Doug Anderson Feb. 25, 2021, 10:57 p.m. UTC | #1
Hi,

On Thu, Feb 25, 2021 at 2:55 PM Konrad Dybcio
<konrad.dybcio@somainline.org> wrote:
>
> Hi,
>
>
> >
> > +&pri_mi2s_active {
> > +     pinconf {
> > +             pins = "gpio53", "gpio54", "gpio55", "gpio56";
> > +             drive-strength = <2>;
> > +             bias-pull-down;
> > +     };
> > +};
> > +
>
> You can omit pinconf{}, so the outcome would be:
> &pri_mi2s_active {
>
>     pins = ...
>
>     ...
>
> };
>
>
> This makes the DTs ever so shorter and is the style that's currently used for new submissions.
>
> Same goes for the nodes that are being referenced.

Yes, I agree.  That definitely makes sense going forward, but I think
it'll just add to the confusion to switch a dts for a given SoC
mid-stride.  ...or, if we do switch the style it should be done in a
separate (no-op) patch series.  This series is already giant enough...

-Doug
Matthias Kaehlcke Feb. 25, 2021, 11:48 p.m. UTC | #2
On Thu, Feb 25, 2021 at 02:12:59PM -0800, Douglas Anderson wrote:
> In general pinconf belongs in board files, not SoC files.  Move it to
> the only current user (trogdor).  Also adjust the drive strengths and
> pulls.
> 
> Cc: V Sujith Kumar Reddy <vsujithk@codeaurora.org>
> Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Cc: Tzung-Bi Shih <tzungbi@chromium.org>
> Cc: Judy Hsiao <judyhsiao@chromium.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
> This should replace the patch ("Asoc: qcom: dts: Change MI2S GPIO
> configuration to pulldown") [1].
> 
> [1] https://lore.kernel.org/r/1605526408-15671-1-git-send-email-srivasam@codeaurora.org
> 
>  arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 24 ++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc7180.dtsi         | 18 ---------------
>  2 files changed, 24 insertions(+), 18 deletions(-)

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Matthias Kaehlcke Feb. 26, 2021, 12:19 a.m. UTC | #3
On Thu, Feb 25, 2021 at 02:13:05PM -0800, Douglas Anderson wrote:
> From: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
> 
> Removed voting for RPMH_RF_CLK2 which is not required as it is
> getting managed by BT SoC through SW_CTRL line.
> 
> Cc: Matthias Kaehlcke <mka@chromium.org>
> Signed-off-by: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Matthias Kaehlcke Feb. 26, 2021, 12:40 a.m. UTC | #4
On Thu, Feb 25, 2021 at 02:13:08PM -0800, Douglas Anderson wrote:
> This is a SKU variant of lazor.  Add it.  This squashes the downstream

> patches to support this hardware.

> 

> NOTES:

> - The non-touch SKU actually has "innolux,n116bca" but that driver is

>   still pending in simple-panel.  The bindings have been Acked though.

>   Things work well enough with the "innolux,n116bge" timings for now,

>   though.

> - The wonky special dts just for "-rev4" arguably doesn't need to go

>   upstream since they weren't widely distributed, but since a few

>   people have them we might as well.  If it ever causes problems we

>   can delete it.

> 

> Cc: Stephen Boyd <swboyd@chromium.org>

> Signed-off-by: Douglas Anderson <dianders@chromium.org>

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Matthias Kaehlcke Feb. 26, 2021, 5:14 p.m. UTC | #5
On Thu, Feb 25, 2021 at 02:13:10PM -0800, Douglas Anderson wrote:
> This is a trogdor variant.  This is mostly a grab from the downstream

> tree with notable exceptions:

> - I skip -rev0.  This was a super early build and there's no advantage

>   of long term support.

> - I remove sound node since sound hasn't landed upstream yet.

> 

> Cc: Gwendal Grignou <gwendal@chromium.org>

> Cc: Matthias Kaehlcke <mka@chromium.org>

> Cc: Stephen Boyd <swboyd@chromium.org>

> Cc: Tzung-Bi Shih <tzungbi@chromium.org>

> Cc: Judy Hsiao <judyhsiao@chromium.org>

> Signed-off-by: Douglas Anderson <dianders@chromium.org>

> ---


Matches downstream except for the sound node and -rev0, which are
mentioned in the commit message. Also looks sane to me otherwise
from a high level inspection.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Stephen Boyd Feb. 26, 2021, 6:45 p.m. UTC | #6
Quoting Douglas Anderson (2021-02-25 14:13:10)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
> new file mode 100644
> index 000000000000..5def9953d82b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
> @@ -0,0 +1,249 @@
[...]
> +
> +/*
> + * There's no SAR sensor, so i2c5 is re-purposed.  We leave the
> + * proximity@28 node under i2c5 (from trogdor.dtsi) since it's "disabled"
> + * and doesn't hurt.
> + */
> +i2c_wlc: &i2c5 {
> +       /* Currently not connected to anything; see b/168652326 */
> +};

Can we remove this? As far as I know this will always be this way and
thus doesn't provide anything meaningful to leave this bug comment here
that doesn't work for people.

> +
> +&i2c7 {
> +       status = "disabled";
> +};
Doug Anderson Feb. 27, 2021, 12:55 a.m. UTC | #7
Hi,

On Fri, Feb 26, 2021 at 10:45 AM Stephen Boyd <swboyd@chromium.org> wrote:
>

> Quoting Douglas Anderson (2021-02-25 14:13:10)

> > diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi

> > new file mode 100644

> > index 000000000000..5def9953d82b

> > --- /dev/null

> > +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi

> > @@ -0,0 +1,249 @@

> [...]

> > +

> > +/*

> > + * There's no SAR sensor, so i2c5 is re-purposed.  We leave the

> > + * proximity@28 node under i2c5 (from trogdor.dtsi) since it's "disabled"

> > + * and doesn't hurt.

> > + */

> > +i2c_wlc: &i2c5 {

> > +       /* Currently not connected to anything; see b/168652326 */

> > +};

>

> Can we remove this? As far as I know this will always be this way and

> thus doesn't provide anything meaningful to leave this bug comment here

> that doesn't work for people.


Yeah, that sounds good.  We just want to delete this whole comment and the node.

That seems like enough reason to repost the series.  I'll plan to do
it early next week.  Of course, I wouldn't object to any of these
things:
* This patch landing and having the node and I'll do a follow-up patch
to remove it.
* Bjorn removing the comment and node as he applies.

-Doug
Dmitry Baryshkov March 14, 2021, 12:28 a.m. UTC | #8
On 26/02/2021 01:12, Douglas Anderson wrote:
> From: Stephen Boyd <swboyd@chromium.org>
> 
> Drop the old node and add the new one in its place.
> 
> Cc: Stephen Boyd <swboyd@chromium.org>
> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
> Cc: Chandan Uddaraju <chandanu@codeaurora.org>
> Cc: Vara Reddy <varar@codeaurora.org>
> Cc: Tanmay Shah <tanmay@codeaurora.org>
> Cc: Rob Clark <robdclark@chromium.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> [dianders: Adjusted due to DP not itself not in upstream dts yet]
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
> 
>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 23 ++++++++++++++++-------
>   1 file changed, 16 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 1ea3344ab62c..60248a6757d8 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -2770,12 +2770,11 @@ usb_1_hsphy: phy@88e3000 {
>   		};
>   
>   		usb_1_qmpphy: phy-wrapper@88e9000 {
> -			compatible = "qcom,sc7180-qmp-usb3-phy";
> +			compatible = "qcom,sc7180-qmp-usb3-dp-phy";
>   			reg = <0 0x088e9000 0 0x18c>,
> -			      <0 0x088e8000 0 0x38>;
> -			reg-names = "reg-base", "dp_com";
> +			      <0 0x088e8000 0 0x38>,

Technically this should be 0x3c. Offset 0x38 is USB3_DP_COM_REVISION_ID3 
(not used by the current driver though).

> +			      <0 0x088ea000 0 0x40>;

I think 0x40 is not enough here.
This is a serdes region and qmp_v3_dp_serdes_tbl contains registers 
0x148 and 0x154.

>   			status = "disabled";
> -			#clock-cells = <1>;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
>   			ranges;
> @@ -2790,7 +2789,7 @@ usb_1_qmpphy: phy-wrapper@88e9000 {
>   				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
>   			reset-names = "phy", "common";
>   
> -			usb_1_ssphy: phy@88e9200 {
> +			usb_1_ssphy: usb3-phy@88e9200 {
>   				reg = <0 0x088e9200 0 0x128>,
>   				      <0 0x088e9400 0 0x200>,
>   				      <0 0x088e9c00 0 0x218>,
> @@ -2803,6 +2802,16 @@ usb_1_ssphy: phy@88e9200 {
>   				clock-names = "pipe0";
>   				clock-output-names = "usb3_phy_pipe_clk_src";
>   			};
> +
> +			dp_phy: dp-phy@88ea200 {
> +				reg = <0 0x088ea200 0 0x200>,
> +				      <0 0x088ea400 0 0x200>,
> +				      <0 0x088eaa00 0 0x200>,
> +				      <0 0x088ea600 0 0x200>,
> +				      <0 0x088ea800 0 0x200>;
> +				#clock-cells = <1>;
> +				#phy-cells = <0>;
> +			};
>   		};
>   
>   		dc_noc: interconnect@9160000 {
> @@ -3166,8 +3175,8 @@ dispcc: clock-controller@af00000 {
>   				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
>   				 <&dsi_phy 0>,
>   				 <&dsi_phy 1>,
> -				 <0>,
> -				 <0>;
> +				 <&dp_phy 0>,
> +				 <&dp_phy 1>;
>   			clock-names = "bi_tcxo",
>   				      "gcc_disp_gpll0_clk_src",
>   				      "dsi0_phy_pll_out_byteclk",
>
Doug Anderson March 15, 2021, 5:40 p.m. UTC | #9
Hi,

On Sat, Mar 13, 2021 at 4:28 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> >               usb_1_qmpphy: phy-wrapper@88e9000 {
> > -                     compatible = "qcom,sc7180-qmp-usb3-phy";
> > +                     compatible = "qcom,sc7180-qmp-usb3-dp-phy";
> >                       reg = <0 0x088e9000 0 0x18c>,
> > -                           <0 0x088e8000 0 0x38>;
> > -                     reg-names = "reg-base", "dp_com";
> > +                           <0 0x088e8000 0 0x38>,
>
> Technically this should be 0x3c. Offset 0x38 is USB3_DP_COM_REVISION_ID3
> (not used by the current driver though).
>
> > +                           <0 0x088ea000 0 0x40>;
>
> I think 0x40 is not enough here.
> This is a serdes region and qmp_v3_dp_serdes_tbl contains registers
> 0x148 and 0x154.

OK!

https://lore.kernel.org/r/20210315103836.1.I9a97120319d43b42353aeac4d348624d60687df7@changeid

-Doug