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[v3,00/12] drm/msm: Add SC8280XP support

Message ID 20221026032624.30871-1-quic_bjorande@quicinc.com
Headers show
Series drm/msm: Add SC8280XP support | expand

Message

Bjorn Andersson Oct. 26, 2022, 3:26 a.m. UTC 
This introduces support for the SC8280XP platform in the MDSS, DPU and
DP driver. It reworks the HDP handling in the DP driver to support
external HPD sources - such as the dp-connector, or USB Type-C altmode.

It then introduces the display clock controllers, mdss, dpu and
displayport controllers and link everything together, for both the MDSS
instances on the platform, and lastly enables EDP on the compute
reference device and 6 of the MiniDP outputs on the automotive
development platform.


The patches was previously sent separately, but submitting them together
here as they (except dts addition) goes in the same tree.

Bjorn Andersson (12):
  dt-bindings: display/msm: Add binding for SC8280XP MDSS
  drm/msm/dpu: Introduce SC8280XP
  dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles
  drm/msm/dp: Stop using DP id as index in desc
  drm/msm/dp: Add DP and EDP compatibles for SC8280XP
  drm/msm/dp: Add SDM845 DisplayPort instance
  drm/msm/dp: Implement hpd_notify()
  drm/msm/dp: Don't enable HPD interrupts for edp
  drm/msm/dp: HPD handling relates to next_bridge
  arm64: dts: qcom: sc8280xp: Define some of the display blocks
  arm64: dts: qcom: sc8280xp-crd: Enable EDP
  arm64: dts: qcom: sa8295-adp: Enable DP instances

 .../bindings/display/msm/dp-controller.yaml   |   3 +
 .../bindings/display/msm/dpu-sc8280xp.yaml    | 287 ++++++
 arch/arm64/boot/dts/qcom/sa8295p-adp.dts      | 244 ++++-
 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts     |  49 +-
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        | 838 ++++++++++++++++++
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 217 +++++
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |   1 +
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  18 +
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |   3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |   2 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       |   1 +
 drivers/gpu/drm/msm/dp/dp_display.c           | 135 +--
 drivers/gpu/drm/msm/dp/dp_drm.c               |   1 +
 drivers/gpu/drm/msm/dp/dp_drm.h               |   2 +
 drivers/gpu/drm/msm/msm_drv.h                 |   1 +
 drivers/gpu/drm/msm/msm_mdss.c                |   2 +
 16 files changed, 1747 insertions(+), 57 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml

Comments

Johan Hovold Oct. 26, 2022, 11:50 a.m. UTC | #1 
On Tue, Oct 25, 2022 at 08:26:24PM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> The SA8295P ADP has, among other interfaces, six MiniDP connectors which
> are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3.
> 
> Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers,
> DP PHYs and link them all together.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---

>  &apps_rsc {
> @@ -156,13 +240,169 @@ vreg_l7g: ldo7 {
>  
>  		vreg_l8g: ldo8 {
>  			regulator-name = "vreg_l8g";
> -			regulator-min-microvolt = <880000>;
> -			regulator-max-microvolt = <880000>;
> +			regulator-min-microvolt = <912000>;
> +			regulator-max-microvolt = <912000>;
> +			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +			regulator-allow-set-load;

Did you really intend to allow set-load here?

I'm guessing this wasn't the case, but otherwise you also need to
specify the valid modes.

> +		};
> +
> +		vreg_l11g: ldo11 {
> +			regulator-name = "vreg_l11g";
> +			regulator-min-microvolt = <912000>;
> +			regulator-max-microvolt = <912000>;
>  			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>  		};
>  	};
>  };

> +&mdss0_dp2_phy {
> +	status = "okay";
> +
> +	vdda-phy-supply = <&vreg_l8g>;
> +	vdda-pll-supply = <&vreg_l3g>;
> +};

Johan
Bjorn Andersson Oct. 27, 2022, 2 a.m. UTC | #2 
On Wed, Oct 26, 2022 at 01:50:15PM +0200, Johan Hovold wrote:
> On Tue, Oct 25, 2022 at 08:26:24PM -0700, Bjorn Andersson wrote:
> > From: Bjorn Andersson <bjorn.andersson@linaro.org>
> > 
> > The SA8295P ADP has, among other interfaces, six MiniDP connectors which
> > are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3.
> > 
> > Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers,
> > DP PHYs and link them all together.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> > ---
> 
> >  &apps_rsc {
> > @@ -156,13 +240,169 @@ vreg_l7g: ldo7 {
> >  
> >  		vreg_l8g: ldo8 {
> >  			regulator-name = "vreg_l8g";
> > -			regulator-min-microvolt = <880000>;
> > -			regulator-max-microvolt = <880000>;
> > +			regulator-min-microvolt = <912000>;
> > +			regulator-max-microvolt = <912000>;
> > +			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> > +			regulator-allow-set-load;
> 
> Did you really intend to allow set-load here?
> 
> I'm guessing this wasn't the case, but otherwise you also need to
> specify the valid modes.
> 

I see no reason for keeping it at this point in time, will drop it.

Thanks,
Bjorn

> > +		};
> > +
> > +		vreg_l11g: ldo11 {
> > +			regulator-name = "vreg_l11g";
> > +			regulator-min-microvolt = <912000>;
> > +			regulator-max-microvolt = <912000>;
> >  			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> >  		};
> >  	};
> >  };
> 
> > +&mdss0_dp2_phy {
> > +	status = "okay";
> > +
> > +	vdda-phy-supply = <&vreg_l8g>;
> > +	vdda-pll-supply = <&vreg_l3g>;
> > +};
> 
> Johan