| Message ID | 20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com |
|---|---|
| Headers | show |
| Series | Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller | expand |
On 9/14/2023 12:29 PM, Kathiravan Thirumoorthy wrote: > Currently mailbox controller takes the XO and APSS PLL as the input. It > can take the GPLL0 also as an input. This patch series adds the same and > fixes the issue caused by this. > > Once the cpufreq driver is up, it tries to bump up the cpu frequency > above 800MHz, while doing so system is going to unusable state. Reason > being, with the GPLL0 included as clock source, clock framework tries to > achieve the required rate with the possible parent and since GPLL0 > carries the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting > changed, causing the issue. > > First half of the series, removes the CLK_SET_RATE_PARENT flag from the > PLL clocks since the PLL clock rates shouldn't be changed. Another > half, add the necessary support to include the GPLL0 as clock provider > for mailbox and accomodate the changes in APSS clock driver. > > This is also the preparatory series to enable the CPUFreq on IPQ5332 > SoC. Dynamic scaling of CPUFreq is not supported on IPQ5332, so to > switch between the frequencies we need to park the APSS PLL in safe > source, here it is GPLL0 and then shutdown and bring up the APSS PLL in > the desired rate. > > For IPQ5332 SoC, this series depends on the below patch > https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/ Bjorn, can this series picked up for v6.7? There is a minor nit the commit message. The statement "APSS PLL will be running at 800MHz" should be "APSS clock / CPU clock will be running at 800MHz" and this should be taken care for clk and the dts patches. Do let me know if I need to re-spin the address to address this. Thanks, > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > --- > Changes in v2: > - included the patch to drop the CLK_SET_RATE_PARENT from IPQ5018 GCC driver > - Splitted the DTS changes per target > - For IPQ8074 and IPQ6018 keep the CLK_SET_RATE_PARENT for UBI32 PLL > since the PLL clock rates can be changed > - Pick up the tags in the relevant patches > - Link to v1: https://lore.kernel.org/r/20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com > > --- > Kathiravan Thirumoorthy (11): > clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks > clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks > clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks > clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks > clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks > dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox > clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider > arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox > arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox > arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox > arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox > > .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- > drivers/clk/qcom/apss-ipq6018.c | 3 +++ > drivers/clk/qcom/gcc-ipq5018.c | 3 --- > drivers/clk/qcom/gcc-ipq5332.c | 2 -- > drivers/clk/qcom/gcc-ipq6018.c | 6 ------ > drivers/clk/qcom/gcc-ipq8074.c | 6 ------ > drivers/clk/qcom/gcc-ipq9574.c | 4 ---- > 11 files changed, 13 insertions(+), 29 deletions(-) > --- > base-commit: e143016b56ecb0fcda5bb6026b0a25fe55274f56 > change-id: 20230913-gpll_cleanup-5d0a339ebd17 > > Best regards,
On Thu, 14 Sep 2023 12:29:50 +0530, Kathiravan Thirumoorthy wrote: > Currently mailbox controller takes the XO and APSS PLL as the input. It > can take the GPLL0 also as an input. This patch series adds the same and > fixes the issue caused by this. > > Once the cpufreq driver is up, it tries to bump up the cpu frequency > above 800MHz, while doing so system is going to unusable state. Reason > being, with the GPLL0 included as clock source, clock framework tries to > achieve the required rate with the possible parent and since GPLL0 > carries the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting > changed, causing the issue. > > [...] Applied, thanks! [01/11] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks commit: e641a070137dd959932c7c222e000d9d941167a2 [02/11] clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks commit: 99cd4935cb972d0aafb16838bb2aeadbcaf196ce [03/11] clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks commit: 01a5e4c6731ab6b4b74822661d296f8893fc1230 [04/11] clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks commit: 99a8f8764b70158a712992640a6be46a8fd79d15 [05/11] clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks commit: 5635ef0bd1052420bc659a00be6fd0c60cec5cb9 [07/11] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider commit: e0e6373d653b7707bf042ecf1538884597c5d0da [08/11] arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox commit: 80ebe63329909531afc87335f1d95c7bf8414438 [09/11] arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox commit: 0133c7af3aa0420778d106cb90db708cfa45f2c6 [10/11] arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox commit: 77c726a4f3b124903db5ced7d597976d5b80dcfb [11/11] arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox commit: da528016952bf93ca810c43fafe518c699db7fa0 Best regards,
Currently mailbox controller takes the XO and APSS PLL as the input. It can take the GPLL0 also as an input. This patch series adds the same and fixes the issue caused by this. Once the cpufreq driver is up, it tries to bump up the cpu frequency above 800MHz, while doing so system is going to unusable state. Reason being, with the GPLL0 included as clock source, clock framework tries to achieve the required rate with the possible parent and since GPLL0 carries the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting changed, causing the issue. First half of the series, removes the CLK_SET_RATE_PARENT flag from the PLL clocks since the PLL clock rates shouldn't be changed. Another half, add the necessary support to include the GPLL0 as clock provider for mailbox and accomodate the changes in APSS clock driver. This is also the preparatory series to enable the CPUFreq on IPQ5332 SoC. Dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch between the frequencies we need to park the APSS PLL in safe source, here it is GPLL0 and then shutdown and bring up the APSS PLL in the desired rate. For IPQ5332 SoC, this series depends on the below patch https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/ Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- Changes in v2: - included the patch to drop the CLK_SET_RATE_PARENT from IPQ5018 GCC driver - Splitted the DTS changes per target - For IPQ8074 and IPQ6018 keep the CLK_SET_RATE_PARENT for UBI32 PLL since the PLL clock rates can be changed - Pick up the tags in the relevant patches - Link to v1: https://lore.kernel.org/r/20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com --- Kathiravan Thirumoorthy (11): clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- drivers/clk/qcom/apss-ipq6018.c | 3 +++ drivers/clk/qcom/gcc-ipq5018.c | 3 --- drivers/clk/qcom/gcc-ipq5332.c | 2 -- drivers/clk/qcom/gcc-ipq6018.c | 6 ------ drivers/clk/qcom/gcc-ipq8074.c | 6 ------ drivers/clk/qcom/gcc-ipq9574.c | 4 ---- 11 files changed, 13 insertions(+), 29 deletions(-) --- base-commit: e143016b56ecb0fcda5bb6026b0a25fe55274f56 change-id: 20230913-gpll_cleanup-5d0a339ebd17 Best regards,