| Message ID | 20240922113351.2390195-1-quic_mdalam@quicinc.com |
|---|---|
| Headers | show |
| Series | Add QPIC SPI NAND driver | expand |
On Sun, Sep 22, 2024 at 05:03:44PM +0530, Md Sadre Alam wrote: > Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. > It can work both in serial and parallel mode and supports typical > SPI-NAND page cache operations. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > --- > > Change in [v10] > > * No change ... > +title: Qualcomm QPIC NAND controller > + > +maintainers: > + - Md sadre Alam <quic_mdalam@quicinc.com> > + > +description: > + The QCOM QPIC-SPI-NAND flash controller is an extended version of > + the QCOM QPIC NAND flash controller. It can work both in serial > + and parallel mode. It supports typical SPI-NAND page cache > + operations in single, dual or quad IO mode with pipelined ECC > + encoding/decoding using the QPIC ECC HW engine. > + > +allOf: > + - $ref: /schemas/spi/spi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - qcom,spi-qpic-snand Recently it turned out that Qualcomm generic compatibles are not generic... That was odd, but to me it is a clear signal that something should not be called generic if it is not generic enough. Please switch to soc-specific compatibles (and drop my reviewed-by, so this will appear in my review queue). Best regards, Krzysztof
On 9/23/2024 2:02 AM, Krzysztof Kozlowski wrote: > On Sun, Sep 22, 2024 at 05:03:44PM +0530, Md Sadre Alam wrote: >> Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. >> It can work both in serial and parallel mode and supports typical >> SPI-NAND page cache operations. >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> --- >> >> Change in [v10] >> >> * No change > > ... > >> +title: Qualcomm QPIC NAND controller >> + >> +maintainers: >> + - Md sadre Alam <quic_mdalam@quicinc.com> >> + >> +description: >> + The QCOM QPIC-SPI-NAND flash controller is an extended version of >> + the QCOM QPIC NAND flash controller. It can work both in serial >> + and parallel mode. It supports typical SPI-NAND page cache >> + operations in single, dual or quad IO mode with pipelined ECC >> + encoding/decoding using the QPIC ECC HW engine. >> + >> +allOf: >> + - $ref: /schemas/spi/spi-controller.yaml# >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,spi-qpic-snand > > Recently it turned out that Qualcomm generic compatibles are not > generic... That was odd, but to me it is a clear signal that something > should not be called generic if it is not generic enough. > > Please switch to soc-specific compatibles (and drop my reviewed-by, so > this will appear in my review queue). Ok , will add in next revision. > > Best regards, > Krzysztof >
v10: * Fixed compilation warnings reported by kernel test robot * Added depends on CONFIG_MTD for qpic-spi nand driver * Removed extra bracket from statement if (i == (num_cw - 1)) in qcom_spi_program_raw() api. v9: * Fixed all the compilation warning reported by kernel test robot * Changed type of cmd1, vld to u32 from __le32 in qcom_nand_controller structure * Changed type of cfg0, cfg1, cfg0_raw, cfg1_raw, clrflashstatus, ecc_buf_cfg, ecc_bch_cfg, clrreadstatus to u32 in qcom_nand_host structure * In nandc_set_read_loc_first() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In nandc_set_read_loc_last() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * Changed data type of cw_offset, read_size, is_last_read_loc to u32 in nandc_set_read_loc() api to fix compilation warning reported by kernel test bot * In set_address() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In update_rw_regs() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_op_cmd_mapping() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_read_status_exec() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_read_id_type_exec() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_misc_cmd_type_exec() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In update_rw_regs() api added cpu_to_le32() macro to fix compilation issue reported by kernel test bot * In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix compilation issue reported by kernel test bot * Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand structure * In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_init() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables reqs, user, step_size, strength and added cpu_to_le32() macro as well to fix compilation warning * In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation warning v8: * Fixed compilation warning reported by kernel test robot * Added "chip" description in nandc_set_read_loc_first() * Added "chip" description" in nandc_set_read_loc_last() * Changed data type of read_location0, read_location1, read_location2, read_location3, addr0, addr1, cmd, cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg, clrflashstatus, clrreadstatus, orig_cmd1, orig_vld to __le32 to fix compilation warning. * Included bitfield.h header file in spi-qpic-snand.c to fix compilation warning * Removed unused variable "steps" variable from qcom_spi_ecc_init_ctx_pipelined() v7: * Added read_oob() and write_oob() api * Added FIELD_PREP() in spi init * Made CONFIG_SPI_QPIC_SNAND and CONFIG_MTD_NAND_QCOM as bool type * Removed offset 0 in oob_ecc() layout * Handled multiple error condition v6: * Added FIELD_PREP() and GENMASK() macro * Added qpic_spi_nand{..} structure for spi nand realted variables * Made qpic_common.c slectable based on either CONFIG_MTD_NAND_QCOM or CONFIG_SPI_QPIC_SNAND * Removed rawnand.h from qpic-common.h * Removed partitions.h and rawnand.h form spi-qpic-snand.c * Added qcom_nand_unalloc() in remove() v5: * Fixes nandbiterr issue * Added raw_read() and raw_write() API * Added qcom_ prefix to all the common API * Removed register indirection * Following tests for SPI-NAND devices passed - mtd_oobtest - mtd_pagetest - mtd_readtest - mtd_speedtest - mtd_stresstest - mtd_subpagetest - mtd_nandbiterrs - nandtest - nanddump - nandwrite - nandbiterr -i - mtd erase - mtd write - dd - hexddump v4: * In this patch series fixes kernel doc for all the cmmon api * Also fixes dm-binding commit message * Fix qpic_common.c compilation based on config v3: * In this patch series fixes multiple things like added clock-name, added _alloc_controller api instead of alloc_master, made common apis more generic etc. * Addressed all the comment from v2 patch series v2: * https://lore.kernel.org/linux-arm-msm/20240215134856.1313239-1-quic_mdalam@quicinc.com/ * In this series of patchs we have added basic working QPIC SPI NAND driver with READ, WRITE, ERASE etc functionality * Addressed all the comments given in RFC [v1] patch v1: * https://lore.kernel.org/linux-arm-msm/20231031120307.1600689-1-quic_mdalam@quicinc.com/ * Initial set of patches for handling QPIC SPI NAND. Md Sadre Alam (8): spi: dt-bindings: Introduce qcom,spi-qpic-snand mtd: rawnand: qcom: cleanup qcom_nandc driver mtd: rawnand: qcom: Add qcom prefix to common api mtd: nand: Add qpic_common API file mtd: rawnand: qcom: use FIELD_PREP and GENMASK spi: spi-qpic: add driver for QCOM SPI NAND flash Interface arm64: dts: qcom: ipq9574: Add SPI nand support arm64: dts: qcom: ipq9574: Disable eMMC node .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 2 +- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 + drivers/mtd/nand/Makefile | 7 + drivers/mtd/nand/qpic_common.c | 738 +++++++ drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/qcom_nandc.c | 1763 +++-------------- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-qpic-snand.c | 1634 +++++++++++++++ include/linux/mtd/nand-qpic-common.h | 482 +++++ 12 files changed, 3349 insertions(+), 1442 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml create mode 100644 drivers/mtd/nand/qpic_common.c create mode 100644 drivers/spi/spi-qpic-snand.c create mode 100644 include/linux/mtd/nand-qpic-common.h