| Message ID | 20240924050941.1251485-1-quic_kshivnan@quicinc.com |
|---|---|
| Headers | show |
| Series | qcom: sc7280: Enable cpucp mbox | expand |
Thanks Dmitry for reviewing the patch On 10/6/2024 10:41 PM, Dmitry Baryshkov wrote: > On Thu, Oct 03, 2024 at 11:13:02AM GMT, Shivnandan Kumar wrote: >> thanks Rob for reviewing this patch. >> >> >> On 9/25/2024 4:55 AM, Rob Herring wrote: >>> On Tue, Sep 24, 2024 at 10:39:39AM +0530, Shivnandan Kumar wrote: >>>> sc7280 has a cpucp mailbox. Document them. >>> >>> And is different from the existing device how? >> >> It is different with respect to the register placement. > > Register placement in the global map or the internal register structure? the register placement varies both internally and globally as well. > >> >> Thanks, >> Shivnandan >> >>> >>>> >>>> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> >>>> --- >>>> .../devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 5 +++-- >>>> 1 file changed, 3 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >>>> index f7342d04beec..4a7ea072a3c1 100644 >>>> --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >>>> +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >>>> @@ -15,8 +15,9 @@ description: >>>> >>>> properties: >>>> compatible: >>>> - items: >>>> - - const: qcom,x1e80100-cpucp-mbox >>>> + enum: >>>> + - qcom,x1e80100-cpucp-mbox >>>> + - qcom,sc7280-cpucp-mbox >>>> >>>> reg: >>>> items: >>>> -- >>>> 2.25.1 >>>> >
On 10/6/2024 8:05 AM, Bjorn Andersson wrote: > On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote: >> Add the CPUCP mailbox node required for communication with CPUCP. > > I'd like to see a description of why that's useful... > I will add in next patch set. > But perhaps more importantly, why are there no user(s) of this? > We will later add features such as BUS DCVS (memlat algorithm in CPUCP) and CPUCP logging based on this series. > Regards, > Bjorn > >> >> Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 3d8410683402..4b9b26a75c62 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 { >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + cpucp_mbox: mailbox@17430000 { >> + compatible = "qcom,sc7280-cpucp-mbox"; >> + reg = <0 0x18590000 0 0x2000>, >> + <0 0x17C00000 0 0x10>; >> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; >> + #mbox-cells = <1>; >> + }; >> + >> system-cache-controller@9200000 { >> compatible = "qcom,sc7280-llcc"; >> reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, >> -- >> 2.25.1 >>
On 17.10.2024 1:51 PM, Shivnandan Kumar wrote: > > > On 10/6/2024 8:05 AM, Bjorn Andersson wrote: >> On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote: >>> Add the CPUCP mailbox node required for communication with CPUCP. >> >> I'd like to see a description of why that's useful... >> > > I will add in next patch set. > >> But perhaps more importantly, why are there no user(s) of this? >> > > We will later add features such as BUS DCVS (memlat algorithm in CPUCP) and CPUCP logging based on this series. I think Bjorn's question here is also "what kind of boards is this going to be useful on", especially given 7280 was more or less released in basically all firmware flavors that we make.. Konrad
On Thu, Oct 17, 2024 at 10:48:32AM +0530, Shivnandan Kumar wrote: > Thanks Dmitry for reviewing the patch > > On 10/6/2024 10:41 PM, Dmitry Baryshkov wrote: > > On Thu, Oct 03, 2024 at 11:13:02AM GMT, Shivnandan Kumar wrote: > > > thanks Rob for reviewing this patch. > > > > > > > > > On 9/25/2024 4:55 AM, Rob Herring wrote: > > > > On Tue, Sep 24, 2024 at 10:39:39AM +0530, Shivnandan Kumar wrote: > > > > > sc7280 has a cpucp mailbox. Document them. > > > > > > > > And is different from the existing device how? > > > > > > It is different with respect to the register placement. > > > > Register placement in the global map or the internal register structure? > > the register placement varies both internally and globally as well. Please mention in the commit message that internal regiter map is different. > > > > > > > > > Thanks, > > > Shivnandan > > > > > > > > > > > > > > > > > Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> > > > > > --- > > > > > .../devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 5 +++-- > > > > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml > > > > > index f7342d04beec..4a7ea072a3c1 100644 > > > > > --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml > > > > > +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml > > > > > @@ -15,8 +15,9 @@ description: > > > > > > > > > > properties: > > > > > compatible: > > > > > - items: > > > > > - - const: qcom,x1e80100-cpucp-mbox > > > > > + enum: > > > > > + - qcom,x1e80100-cpucp-mbox > > > > > + - qcom,sc7280-cpucp-mbox > > > > > > > > > > reg: > > > > > items: > > > > > -- > > > > > 2.25.1 > > > > > > >
This series enables CPUCP mailbox support on the SC7280 SoC, facilitating communication between Linux and the CPUCP firmware. Shivnandan Kumar (3): dt-bindings: mailbox: qcom,cpucp-mbox: Add sc7280 cpucp mailbox instance mailbox: qcom-cpucp-mbox: Add support for SC7280 CPUCP mailbox controller arm64: dts: qcom: sc7280: Add cpucp mbox node .../bindings/mailbox/qcom,cpucp-mbox.yaml | 5 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 + drivers/mailbox/qcom-cpucp-mbox.c | 156 ++++++++++++++---- 3 files changed, 133 insertions(+), 36 deletions(-) -- 2.25.1