From patchwork Wed Oct 9 07:41:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 834067 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63E6113A409; Wed, 9 Oct 2024 07:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728459730; cv=none; b=QVeSSOraDVI3HrHlYGr0m5nM9bY8C86LyJ3icK3CSUz2Iypawp54pM1Mg/m4szT8XyKVjdLCggTVCMm+Pg3rf949iGo/VcXwbeU3EWFXKH9z1wWTdUaGaeGsNVtSmbZ4oAdwzg5c6ZbdX0BWs/HacpA3QggnXzdMe+TC+afhBeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728459730; c=relaxed/simple; bh=CyyiE0jRGphoz/rcgGrg436VnyQp/QMVRyfnTGhKg3g=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Turp3HNYXANm02VM22rz82m5EXY7dGjqk+HUR+n0miAiEo28xA3qwtgjhNJ9cxPQ8oAfQcmHZxiVIo60Xr0y0egfWXtm+A+VvdjeYumaeQ4HYKBcsFluWhGVJIkatBynSpbhKMFf4ZFd57/6jyP0Q76TKuo+4eC5B3j68P20xX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kTn4uDNn; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kTn4uDNn" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 498Nj9Mm000694; Wed, 9 Oct 2024 07:41:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=OjvSXWvuHNP3INf44TdQlC EVcGlQf/PH5Zq7trzJbBo=; b=kTn4uDNnYhPnvDqDugOs1AQHEKAEv6X0iJX9i8 /JP4qJEBf4iYQx/qPtkK12d0j+UhwXGmLUCBhomypfvDqEKs53NCPPngy+M1YKg3 ClOh9Hq2N278tpFTC4YJSIett6pbPuMvJe7LtkEwtNU4w8eNNeFpZldcO2u7i6xD v8MJUIlO7SzpBQX359Gmr+xeW9HEQmIC6FHFO/dKDczBFwkJadZyjYrE/cWbaHnD 8/zalHGqT3UifKDoXKGX6czg4aeeHyp+/xKmNyBIJ4iBtGL4P6KCpnLmyOcwlvzl 4meUeFEOfUDuPRKzIw62+gljpUijnkqWooJ/dHsHtvQ4z4sg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4252wsu06t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 07:41:50 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4997fn0J019085 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 07:41:49 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 00:41:42 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v7 0/6] Add NSS clock controller support for IPQ9574 Date: Wed, 9 Oct 2024 13:11:19 +0530 Message-ID: <20241009074125.794997-1-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: C2CCtANBlbKyPBNyGyeb5XfyCToTCgAH X-Proofpoint-GUID: C2CCtANBlbKyPBNyGyeb5XfyCToTCgAH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=798 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090049 Add bindings, driver and devicetree node for networking sub system clock controller on IPQ9574. Also add support for gpll0_out_aux clock which serves as the parent for some nss clocks. This series depends on the below patch which adds support for NSS Huayra alpha pll https://lore.kernel.org/linux-arm-msm/20241004102342.2414317-2-quic_srichara@quicinc.com/ Changes in V7: - Drop the 1st patch because it's posted as part of the IPQ5424 minimal boot support series [1] 1. https://lore.kernel.org/linux-arm-msm/20241004102342.2414317-1-quic_srichara@quicinc.com/ - Detailed change logs are added to the respective patches. V6 can be found at: https://lore.kernel.org/linux-arm-msm/20241004080332.853503-1-quic_mmanikan@quicinc.com/ V5 can be found at: https://lore.kernel.org/linux-arm-msm/20240626143302.810632-1-quic_devipriy@quicinc.com/ V4 can be found at: https://lore.kernel.org/linux-arm-msm/20240625070536.3043630-1-quic_devipriy@quicinc.com/ V3 can be found at: https://lore.kernel.org/linux-arm-msm/20240129051104.1855487-1-quic_devipriy@quicinc.com/ V2 can be found at: https://lore.kernel.org/linux-arm-msm/20230825091234.32713-1-quic_devipriy@quicinc.com/ Devi Priya (6): dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions clk: qcom: Add NSS clock Controller driver for IPQ9574 arm64: dts: qcom: ipq9574: Add nsscc node arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 .../bindings/clock/qcom,ipq9574-nsscc.yaml | 74 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 23 + arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9574.c | 15 + drivers/clk/qcom/nsscc-ipq9574.c | 3084 +++++++++++++++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 + .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 + 10 files changed, 3492 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h