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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a00007078sm821563e87.212.2024.10.17.09.57.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 09:57:03 -0700 (PDT) From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Subject: [PATCH 00/14] clk: qcom: add support for clock controllers on the SAR2130P platform Date: Thu, 17 Oct 2024 19:56:50 +0300 Message-Id: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIANJBEWcC/x3MTQqAIBBA4avErBPUjKirRAt/xhoKDQciiO6et PwW7z3AWAgZpuaBghcx5VSh2gb8ZtOKgkI1aKmNkmoQbItWnTyFP7LfWfTRhTC6KA0i1OosGOn +j/Pyvh8xlu7xYQAAAA== X-Change-ID: 20241017-sar2130p-clocks-5fbdd9bf04ee To: Bjorn Andersson <andersson@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Taniya Das <quic_tdas@quicinc.com>, Neil Armstrong <neil.armstrong@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Konrad Dybcio <konradybcio@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kalpak Kawadkar <quic_kkawadka@quicinc.com>, Konrad Dybcio <konradybcio@kernel.org> X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2707; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=OAZejn9mCT0AFo77p3qhjE8gA31X50sk9TKnxj1/KOQ=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnEUHYFVQMVMHSbHTOAHD1NZ0f1npaoX8xSe/jX dHtb1j+T1iJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxFB2AAKCRAU23LtvoBl uHflD/oDv9yr4s6KsV+BENXK65lQFt1Bt2DFxk436NTmthVQwS32VFoq+gxnKUQzP5tSkfsOl/C kmYcFTeyjAD+LraC9YAVoHrkZMWZWU+IzzSZe++Mnku1XS0B0KiL8JLOhRz41cs4zpJn0mExTqE vAhiPMkVsCmK3sEzysjlrPhNZIwzRlLnERGukVZzfuQ78AWS7Dy+3U/jCLrpDPEV3ReF6bdMOj1 Op3u1kLNO5J3kNGX4M7C45ZnePfvVUMHVzSnDz7U611xAW8aSPIunkB6L9kO/6VFwQNX1WRC19E q884PyTZcpQcyGfmyJzCY2gBxbHG22xkdWyDoj3/L8t0fuDYs6HKCnMsPNPY9EIusDzru3bHIJh anskGw4iMzlksC7D/pZGQhHdb0Pq1mcMsb6qqcwrhDuA/VL1+dqLn2iOqjzf4IincE8GnqMETJY Mwt0SuqTBAir9HZwjoDaCOA8oTMozKQDJ49M3poNst9r7pZYh8PZIilWPcc8N4tltbJRZzhfcJh 20jBfR5NXp3lg1zxm9CVTEeh1p3hiuZWaSt1Krc5njvsxiq/cexFapu5ODNZdvjEsi3ehHCP3UI S1v+qDxUhxNXHVV3ENcpJPeSmBwYLdMM3fwtewkg6Qjkmxn6ugoDasLfPX3AmtXfExd7tFsN4Xi tBBBwwLynkNQuEg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A |
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clk: qcom: add support for clock controllers on the SAR2130P platform
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Add support for the RPMh, TCSR, Global, Display and GPU clock controllers as present on the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Dmitry Baryshkov (10): dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible dt-bindings: clock: qcom: document SAR2130P Global Clock Controller dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible clk: qcom: rcg2: add clk_rcg2_shared_floor_ops clk: qcom: gdsc: add separate sleep state collapse vote support clk: qcom: rpmh: add support for SAR2130P clk: qcom: add support for GCC on SAR2130P clk: qcom: tcsrcc-sm8550: add SAR2130P support clk: qcom: dispcc-sm8550: enable support for SAR2130P Kalpak Kawadkar (2): clk: qcom: clk-branch: Add support for BRANCH_HALT_POLL flag clk: qcom: clk-branch: Add support for SREG branch ops Konrad Dybcio (2): dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles clk: qcom: add SAR2130P GPU Clock Controller support .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + .../bindings/clock/qcom,sar2130p-gcc.yaml | 65 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + .../bindings/clock/qcom,sm8550-dispcc.yaml | 1 + .../bindings/clock/qcom,sm8550-tcsr.yaml | 1 + drivers/clk/qcom/Kconfig | 22 +- drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/clk-branch.c | 39 +- drivers/clk/qcom/clk-branch.h | 5 + drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 48 +- drivers/clk/qcom/clk-rpmh.c | 11 + drivers/clk/qcom/dispcc-sm8550.c | 18 +- drivers/clk/qcom/gcc-sar2130p.c | 2463 ++++++++++++++++++++ drivers/clk/qcom/gdsc.c | 8 + drivers/clk/qcom/gdsc.h | 2 + drivers/clk/qcom/gpucc-sar2130p.c | 507 ++++ drivers/clk/qcom/tcsrcc-sm8550.c | 18 +- include/dt-bindings/clock/qcom,sar2130p-gcc.h | 181 ++ include/dt-bindings/clock/qcom,sar2130p-gpucc.h | 33 + include/dt-bindings/reset/qcom,sar2130p-gpucc.h | 14 + 21 files changed, 3430 insertions(+), 12 deletions(-) --- base-commit: 7df1e7189cecb6965ce672e820a5ec6cf499b65b change-id: 20241017-sar2130p-clocks-5fbdd9bf04ee Best regards,