mbox series

[v1,00/10] Enable cpufreq for IPQ5332 & IPQ9574

Message ID cover.1693996662.git.quic_varada@quicinc.com
Headers show
Series Enable cpufreq for IPQ5332 & IPQ9574 | expand

Message

Varadarajan Narayanan Sept. 7, 2023, 5:21 a.m. UTC 
Depends On:
https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/
https://lore.kernel.org/linux-arm-msm/20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com/

This patch series aims to enable cpufreq for IPQ5332 and IPQ9574.
For IPQ5332, a minor enhancement to Stromer Plus ops and a safe
source switch is needed before cpu freq can be enabled.

These are also included in this series. Posting this as a single
series. Please let me know if this is not correct, will split in
the subsequent revisions.

Passed the following DT related validations
make W=1 ARCH=arm64 -j16 DT_CHECKER_FLAGS='-v -m' dt_binding_check DT_SCHEMA_FILES=qcom
make W=1 ARCH=arm64 -j16 CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check

For IPQ5332:
~~~~~~~~~~~
	* This patch series introduces stromer plus ops which
	  builds on stromer ops and implements a different
	  set_rate and determine_rate.

	  A different set_rate is needed since stromer plus PLLs
	  do not support dynamic frequency scaling. To switch
	  between frequencies, we have to shut down the PLL,
	  configure the L and ALPHA values and turn on again. So
	  introduce the separate set of ops for Stromer Plus PLL.

	* Update ipq_pll_stromer_plus to use clk_alpha_pll_stromer_plus_ops
	  instead of clk_alpha_pll_stromer_ops.

	* Set 'l' value to a value that is supported on all SKUs.

	* Provide safe source switch for a53pll

	* Include IPQ5332 in cpufreq nvmem framework

	* Add OPP details to device tree

For IPQ9574:
~~~~~~~~~~~
	* Include IPQ9574 in cpufreq nvmem framework

	* Add OPP details to device tree

Varadarajan Narayanan (10):
  clk: qcom: clk-alpha-pll: introduce stromer plus ops
  clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
  clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
  clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
  dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ5332
  cpufreq: qti: Enable cpufreq for ipq53xx
  arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse
  dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ9574
  cpufreq: qti: Introduce cpufreq for ipq95xx
  arm64: dts: qcom: ipq9574: populate the opp table based on the eFuse

 .../bindings/cpufreq/qcom-cpufreq-nvmem.yaml       |  2 +
 arch/arm64/boot/dts/qcom/ipq5332.dtsi              | 34 ++++++++++-
 arch/arm64/boot/dts/qcom/ipq9574.dtsi              | 38 +++++++++++-
 drivers/clk/qcom/apss-ipq-pll.c                    |  4 +-
 drivers/clk/qcom/apss-ipq6018.c                    | 54 ++++++++++++++++-
 drivers/clk/qcom/clk-alpha-pll.c                   | 68 ++++++++++++++++++++++
 drivers/clk/qcom/clk-alpha-pll.h                   |  1 +
 drivers/cpufreq/cpufreq-dt-platdev.c               |  2 +
 drivers/cpufreq/qcom-cpufreq-nvmem.c               | 35 +++++++++++
 9 files changed, 231 insertions(+), 7 deletions(-)