From patchwork Mon Jan 4 13:49:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356381 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978547jai; Mon, 4 Jan 2021 05:42:52 -0800 (PST) X-Google-Smtp-Source: ABdhPJxX+rI/oKJJtqr64lGvOEZRebfpxP7VyuikZqVQQBkSjIpjYwndgknQLDetZAVAtk0UVZl5 X-Received: by 2002:a17:906:f153:: with SMTP id gw19mr68157090ejb.272.1609767772129; Mon, 04 Jan 2021 05:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767772; cv=none; d=google.com; s=arc-20160816; b=ijeT3a3SobX+oSSv1dxaC2dXw79/A8ofU+X5E68X56k6bwrCvqKHwllz/Hd4yLhJzT JHj6ZoeQsCwCIaKZXe2u+H/Il8gyiOeS8q8Q8qI0Cql8YnfmKvUeyDUVY9ijGmIMkt5s lbxHfzrd5O2nPYJ5x515HvwUhCd5Szml2KV5xvkBAzGgX9hf0eWhrSa5hvkG3lD4VxcF cr9rW3Mnfmm36go4U4hew8gAYMKU/sZhD2c5idSIiJjNV9vQV40ZL1hrDsynHB3bHYDu RerdColBHBCTX2yJ+IPda2XazhYb3O9m0QiL+Q3jYNopYc2Fw5Zlnw639lQE0QJK3zy1 8f3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=07rDU/OuVJvk6JF93jkdN2tmY83mHUDzBU2a1fn2P0w=; b=PwDxa1yR487r7EqfSYHvHT2UzfEdaV/GhFU5BAFnhMcUS0iy7EaYwSGbwjmn4GTRoV q5QX8JRMxRQt+wEBwcdtgigIcp2QkeOyJRSsP0hTWMkyambimn5zayL4pEqhpss3Dgue 6sf4vgH8k3rDZUNxpsQeRNU4qHmjyGnBks4OP/2/aQQd3mtF9NmkVrgiZPHo8Me5e8+V VWtiUtne+CKF4/uqFQsQgWrEF2eRO5lEXohzWYW7h+KizBy1zvx78S6TTsg+A+CGQr+5 D3iCY2MLM2P4jA0u0quDKCUZinQDudDzxdO1r52mJJQKM8d2IkFziaZ6Ihqm9P9afKlz 2E8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/0aQMuT"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.42.51; Mon, 04 Jan 2021 05:42:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/0aQMuT"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726640AbhADNmv (ORCPT + 15 others); Mon, 4 Jan 2021 08:42:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbhADNmv (ORCPT ); Mon, 4 Jan 2021 08:42:51 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6A85C061794 for ; Mon, 4 Jan 2021 05:42:10 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id k10so18503705wmi.3 for ; Mon, 04 Jan 2021 05:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=07rDU/OuVJvk6JF93jkdN2tmY83mHUDzBU2a1fn2P0w=; b=l/0aQMuTQBAkPOZSm08RmdSm1kqoPxvPBl8+byeCXJuumKsmV7g/OKSTYLCtnQUxDO 17JxJiiI8zweDO/K+6s9g83X/5T3A/CaoqIjmFJd/AY3eerFXN2aHu60wcKMHgFxwRIu zHouXN+yMPWIHfWMELCP/J8Ec4OL8QowQMY/mCBGWOJXZNecyJLWMZa2/BPCXAs4Mpud qPYphRh/LEBs+PIEn0OV6Uis7aIVMRE/Y8swRHVYKi/2Tw6aBIEH3Uzi4Glz1F6D3V0G O6Opz+5jDwpWbZbPqYcUZFHOeynzYJGLSQydnl4YMsQVk8N737R72TFy4q55BHMlBDPk d/eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=07rDU/OuVJvk6JF93jkdN2tmY83mHUDzBU2a1fn2P0w=; b=awWkFCPSQtTyIFZaEwo2+hFsh4TWaLb3ibZUaQrT2XcMiq7BPnMH0ELzoll5Osehaa dqs7nMaCEyNaZsOud9FrBKey1rLAuZZZ7HJlZ6Dy10+qGWdEnmltnThqojUKauB4uVAx sbQCgO82TibqHkvzCoDMFb7zcuOlRNL18U5sYkfy5p74Ogb/BmJtEuij/GZCEUe7Hg4e HVicjHdvPIbgXolAyAm2ndpNNVSgXCTLgIZrjk8zv/tYEQEVV5+C2xnRj3AuSb5tdKpd Os2eMjti8/A2wSor4zwNpUAygWMWOWm/+73oBYpBqNDTt3O8sURVzBpdBNcsn11uWilq a84w== X-Gm-Message-State: AOAM531+MTSoWR61XBq6LFecHa4d5CsSzIQ73AyZqnUiA713VCiomo36 eNx0GwOhKTwFa8QNkHPW8sRjGQ== X-Received: by 2002:a1c:9ac6:: with SMTP id c189mr27075961wme.137.1609767729368; Mon, 04 Jan 2021 05:42:09 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:08 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 01/10] bus: mhi: core: Add device hardware reset support Date: Mon, 4 Jan 2021 14:49:30 +0100 Message-Id: <1609768179-10132-2-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MHI specification allows to perform a hard reset of the device when writing to the SOC_RESET register. It can be used to completely restart the device (e.g. in case of unrecoverable MHI error). This is up to the MHI controller driver to determine when this hard reset should be used, and in case of MHI errors, should be used as a reset of last resort (after standard MHI stack reset). This function is a stateless function, the MHI layer do nothing except triggering the reset by writing into the right register(s), this is up to the caller to ensure right mhi_controller state (e.g. unregister the controller if necessary). Signed-off-by: Loic Poulain --- drivers/bus/mhi/core/main.c | 13 +++++++++++++ include/linux/mhi.h | 9 +++++++++ 2 files changed, 22 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index a353d1e..c181a85 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -142,6 +142,19 @@ enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) } EXPORT_SYMBOL_GPL(mhi_get_mhi_state); +void mhi_soc_reset(struct mhi_controller *mhi_cntrl) +{ + if (mhi_cntrl->reset) { + mhi_cntrl->reset(mhi_cntrl); + return; + } + + /* Generic MHI SoC reset */ + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, + MHI_SOC_RESET_REQ); +} +EXPORT_SYMBOL_GPL(mhi_soc_reset); + int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info) { diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 04cf7f3..7ddbcd7 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -355,6 +355,7 @@ struct mhi_controller_config { * @unmap_single: CB function to destroy TRE buffer * @read_reg: Read a MHI register via the physical link (required) * @write_reg: Write a MHI register via the physical link (required) + * @reset: Controller specific reset function (optional) * @buffer_len: Bounce buffer length * @index: Index of the MHI controller instance * @bounce_buf: Use of bounce buffer @@ -445,6 +446,7 @@ struct mhi_controller { u32 *out); void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val); + void (*reset)(struct mhi_controller *mhi_cntrl); size_t buffer_len; int index; @@ -681,6 +683,13 @@ enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl); /** + * mhi_soc_reset - Trigger a device reset. This can be used as a last resort + * to reset and recover a device. + * @mhi_cntrl: MHI controller + */ +void mhi_soc_reset(struct mhi_controller *mhi_cntrl); + +/** * mhi_device_get - Disable device low power mode * @mhi_dev: Device associated with the channel */