From patchwork Mon Jan 4 13:49:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356383 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978568jai; Mon, 4 Jan 2021 05:42:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJzXFDwoxs9P1cZAxD1TKBE6x7fOqkQdiXZHaGZjaKEzOw6QKCBTG+wnvjuaS63GunJz02ek X-Received: by 2002:a17:906:ae14:: with SMTP id le20mr68523528ejb.451.1609767773880; Mon, 04 Jan 2021 05:42:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767773; cv=none; d=google.com; s=arc-20160816; b=zRwEqoYJFHNm3Y4sQBYeN/rvnAU8CihBhYhDCtqifsZDQmZqfmlII1VLFXUimmLRUa 2GQxZj3brU3sCVaUJ6SFi826RIDrJJ0K3Nt1LMGDfjeJL/WmBP9ZB7WNyi6TV5QD3Q5M LZkEvf0YonmG5JWOsEoiLgMN44sOYlwy7mm2EE2xjOyf8XfZ5Y4S0WP7cwvqtZ8MzRKr z7b6Burvb/9yR5C/GVuBlSYFWTVzKVT4rWHplE6VYgQD4N7kjwpakyAlzNfQVWUPaV/V l13bDGi48PdQm03m+5x2W/Sq7UOkpse6RkDo64+KW26PuPUn6fS/XMRGokZzOCjFX/vA bP5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=MkeCdMAJPZmLxc6YEqvhWKBD6uPygtoaXQQ7bd/Z3b9d72x4R/oeJQjyP1I4LaReFN DbyfZFPLuLLS0JJ/BfYFOuzzzRS3mwMSq5j4Bvl0LC9r6/72e9LDbXxZvUA8NBuIWPUz K/ZCWvPUU8jlrhn7sOA2+rLxTPKErQxssrG1Fi+CCvH8iry2POwrLxRsportbnMc5g7J yy4P+e6paNsG6h1Tl7xlXQFsSaC/MqNHVTW3rz3yQxQ237u0juCy3g4Mplbdsc4vWjre KYVIFhgTS0519xs0+UHtzq7YrS1ByWIFI3pQ2rCILzFKWczShUksp4qZGPu1Gz7JSp7R MUCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ij9S+uxC; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.42.53; Mon, 04 Jan 2021 05:42:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ij9S+uxC; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726663AbhADNmx (ORCPT + 15 others); Mon, 4 Jan 2021 08:42:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbhADNmw (ORCPT ); Mon, 4 Jan 2021 08:42:52 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65DEFC061796 for ; Mon, 4 Jan 2021 05:42:12 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id q75so19358200wme.2 for ; Mon, 04 Jan 2021 05:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=Ij9S+uxCQOB8AB3yESR3oc43wm/FoqRTkJXriq4dF1yk/BLFqfvlm1jHCaQnNyz1Aj od5JJMa9vFwX0+ZpgDDv/f0iJN20OjYMo3GmdsVdJJEPHiTYzOQeasUmvfxNZ+rVnbG/ TZ/e/X9/7qh6Up6nBWfKRR1lT3pv/v5Z/8PMNSrvdLEC8ZSTlzBDgaAoHy1t2MX+k92T 1jj0EXvagGel6P/PMAkLnH78nVq8HGYxFrF7DsVFqNEb/4NfCB9IsQ+6fgTSJkHF8pe5 h7TYRu69Ko0Nrw+QXoGysqnF3zJHFISAgEuqxKhCwTFAHvr7jYfyfUOZJifIWKAf9Q3Q oeTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=AStMVZVNL8ZO1uK8CcQwuC0ll9akSvE9k5V8JF5rWZdPHO2kwrZb/ODrqnA40wMG8z YyCql9kgiWSVvC687yx2rY7dGRhTeIPRTdR0ZyGEKnuSCQNDxFRlOmFC8myzy/BRQJPf lekoxSgRfvMrxYVily2NCGqsU/nU9uoDqlj9nyBz55+lNy09UmExYlfUTEapNrDcH9oH q9WZYkeAFiM6fGbVYP1qZsbdKHNQRFGy9K6u+8iWJq119jJlwbbyi2Mrj4WSn4+sxDhu DQvDMeFaGTFcUSegIdIbENdjSgTz9Jt3PMex6UlcZJwxTk1bTguR3Z0LsIBLqNJOWfll Qpxw== X-Gm-Message-State: AOAM531/4H7cxFGfPK8cZAtl/4u0laAKTvbs7fIX9Iw+TflK+qPBc17d GQcHCUztMoYaIFB5hNesSWL+wIFNyNTYQy/Q X-Received: by 2002:a1c:1dd4:: with SMTP id d203mr27331101wmd.118.1609767731127; Mon, 04 Jan 2021 05:42:11 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:10 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 03/10] mhi: pci_generic: Enable burst mode for hardware channels Date: Mon, 4 Jan 2021 14:49:32 +0100 Message-Id: <1609768179-10132-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hardware channels have a feature called burst mode that allows to queue transfer ring element(s) (TRE) to a channel without ringing the device doorbell. In that mode, the device is polling the channel context for new elements. This reduces the frequency of host initiated doorbells and increase throughput. Create a new dedicated macro for hardware channels with burst enabled. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 13a7e4f..077595c 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -76,6 +76,36 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } \ + +#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring) \ { \ .num_elements = 128, \ @@ -110,8 +140,8 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = {