From patchwork Wed Jun 28 12:34:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 698075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6412FEB64DA for ; Wed, 28 Jun 2023 12:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232330AbjF1Mk4 (ORCPT ); Wed, 28 Jun 2023 08:40:56 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]:60112 "EHLO mx0b-0031df01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231810AbjF1Mho (ORCPT ); Wed, 28 Jun 2023 08:37:44 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35SCTnM0024262; Wed, 28 Jun 2023 12:37:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=nPaAz0ocSxAKTJs7RTIRBsUIrURO8wj1m2EtWn9n8x0=; b=n0gbiQvzk0b/pg89AVjzh7Ia7Tpn59q5IKkwogaNPc1ImYWlze5VxD8CtMAoVP8VVIVo /4fEuGOaCgWzEOnyFJK8biLaAgXpsiajWrdL1RvLL5W8nWDE9jlv/kNj46YUrHKgbLzH z3pCVGQYoRnOM4y8q7YLxYSgsDoyS0jiMGRr4yFaVITibOTJIRF7A2bONHSJdfHdUKRQ DfmvLmI23zZIL0c8VavgYj0mPrd7C6d4nEHH1HWJJit1X12Q5CWjUNvsk46DQMtE1lyW Auq+yNGchg5zBlajqxPmSENF1zqiPdwuS+eFy+PIYi4VM8Kfj9XKXXw1Z60XLFbqSqm6 +g== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rgemk0x8a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Jun 2023 12:37:27 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35SCbQ4m028510 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Jun 2023 12:37:26 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 28 Jun 2023 05:37:19 -0700 From: Mukesh Ojha To: , , , , , , , , , , , , , , CC: , , , , , , , , "Mukesh Ojha" Subject: [PATCH v4 19/21] firmware: scm: Modify only the download bits in TCSR register Date: Wed, 28 Jun 2023 18:04:46 +0530 Message-ID: <1687955688-20809-20-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1687955688-20809-1-git-send-email-quic_mojha@quicinc.com> References: <1687955688-20809-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rZep0ltKHpRUsYbklWWZe3bUwLAa3_a2 X-Proofpoint-ORIG-GUID: rZep0ltKHpRUsYbklWWZe3bUwLAa3_a2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-28_08,2023-06-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306280111 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org CrashDump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance. Co-developed-by: Poovendhan Selvaraj Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom_scm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 104d86e49b97..a9ff77d16c42 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -30,6 +30,11 @@ module_param(download_mode, bool, 0); #define SCM_HAS_IFACE_CLK BIT(1) #define SCM_HAS_BUS_CLK BIT(2) +#define QCOM_DOWNLOAD_FULLDUMP 0x1 +#define QCOM_DOWNLOAD_NODUMP 0x0 +#define QCOM_DOWNLOAD_MODE_SHIFT 4 +#define QCOM_DOWNLOAD_MODE_MASK 0x30 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -440,6 +445,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) static void qcom_scm_set_download_mode(bool enable) { bool avail; + int val; int ret = 0; avail = __qcom_scm_is_call_available(__scm->dev, @@ -448,8 +454,10 @@ static void qcom_scm_set_download_mode(bool enable) if (avail) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else if (__scm->dload_mode_addr) { - ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + val = (enable ? QCOM_DOWNLOAD_FULLDUMP : QCOM_DOWNLOAD_NODUMP); + val <<= QCOM_DOWNLOAD_MODE_SHIFT; + ret = qcom_scm_io_update_field(__scm->dload_mode_addr, + QCOM_DOWNLOAD_MODE_MASK, val); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n");