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Fri, 05 Jan 2018 09:10:05 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id g17sm3263661wra.6.2018.01.05.09.10.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Jan 2018 09:10:04 -0800 (PST) From: Jerome Brunet To: Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org Cc: Jerome Brunet , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Vladimir Zapolskiy , Sylvain Lemieux , Andy Gross , David Brown Subject: [PATCH 2/5] clk: lpc32xx: read-only divider can propagate rate change Date: Fri, 5 Jan 2018 18:09:56 +0100 Message-Id: <20180105170959.17266-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180105170959.17266-1-jbrunet@baylibre.com> References: <20180105170959.17266-1-jbrunet@baylibre.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the register shall be left un-touched, but it does not mean the clock should stop rate propagation if CLK_SET_RATE_PARENT is set This properly handled in qcom clk-regmap-divider but it was not in the lpc32xx divider Fixes: f7c82a60ba26 ("clk: lpc32xx: add common clock framework driver") Signed-off-by: Jerome Brunet --- drivers/clk/nxp/clk-lpc32xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index f5d815f577e0..729333766f97 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -963,6 +963,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); unsigned int bestdiv; /* if read only, just return current value */ @@ -972,6 +973,15 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, bestdiv &= div_mask(divider->width); bestdiv = _get_div(divider->table, bestdiv, divider->flags, divider->width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!hw_parent) + return -EINVAL; + + *prate = clk_hw_round_rate(hw_parent, rate * bestdiv); + } + return DIV_ROUND_UP(*prate, bestdiv); }