From patchwork Sat Oct 10 03:28:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernard Zhao X-Patchwork-Id: 285083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81A95C433E7 for ; Sat, 10 Oct 2020 04:05:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4810F2074D for ; Sat, 10 Oct 2020 04:05:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726541AbgJJEEe (ORCPT ); Sat, 10 Oct 2020 00:04:34 -0400 Received: from mail-m17613.qiye.163.com ([59.111.176.13]:33584 "EHLO mail-m17613.qiye.163.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730883AbgJJDgG (ORCPT ); Fri, 9 Oct 2020 23:36:06 -0400 X-Greylist: delayed 339 seconds by postgrey-1.27 at vger.kernel.org; Fri, 09 Oct 2020 23:36:05 EDT Received: from ubuntu.localdomain (unknown [157.0.31.124]) by mail-m17613.qiye.163.com (Hmail) with ESMTPA id A04B4482738; Sat, 10 Oct 2020 11:29:05 +0800 (CST) From: Bernard Zhao To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Bernard Zhao , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: opensource.kernel@vivo.com Subject: [PATCH] drm/msm/disp: add error value record in for circle`s error index Date: Fri, 9 Oct 2020 20:28:56 -0700 Message-Id: <20201010032858.4441-1-bernard@vivo.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgYFAkeWUFZS1VLWVdZKFlBSE83V1ktWUFJV1kPCR oVCBIfWUFZHxpOT0sfHx0dGUlDVkpNS0lIS0tOT05DTUpVEwETFhoSFyQUDg9ZV1kWGg8SFR0UWU FZT0tIVUpKS0hKQ1VLWQY+ X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OFE6DQw*Nz8eS0NDDhwNPUg2 L08KCxFVSlVKTUtJSEtLTk9NSEtOVTMWGhIXVRkeCRUaCR87DRINFFUYFBZFWVdZEgtZQVlKTkxV S1VISlVKSU9ZV1kIAVlBSU1ISDcG X-HM-Tid: 0a75108e0b2d93bakuwsa04b4482738 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In function dpu_core_irq_enable & dpu_core_irq_disable, when some index enable or disable failed, return value will be covered by next success index. Upper call function will not catch this error, this maybe does not meet the expectation. This change is to make the code a bit more readable. Signed-off-by: Bernard Zhao --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index f1bc6a1af7a7..e6da0469b743 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -123,8 +123,8 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); for (i = 0; (i < irq_count) && !ret; i++) - ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]); - + if (_dpu_core_irq_enable(dpu_kms, irq_idxs[i]) != 0) + ret = -EINVAL; return ret; } @@ -178,8 +178,8 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); for (i = 0; (i < irq_count) && !ret; i++) - ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]); - + if (_dpu_core_irq_disable(dpu_kms, irq_idxs[i]) != 0) + ret = -EINVAL; return ret; }