From patchwork Thu Dec 3 14:20:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336935 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332701ilb; Thu, 3 Dec 2020 06:23:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJzrMIMMlb+FsRKrvHBT0oItx1FrSSVZKYWwxVSAJrg+aLsueEIFOrXuoIIuijCrAG2Y3Zjh X-Received: by 2002:a50:e715:: with SMTP id a21mr3033712edn.285.1607005400175; Thu, 03 Dec 2020 06:23:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607005400; cv=none; d=google.com; s=arc-20160816; b=jrHZP94ac3yMuAb9FCPUdz8BApTtlKVatus68IUhdincB0sio2Bq+I+hQ1lDJ7i0v5 zSD/yBP1CRO8iB7NHXgj9rcZ208fHMIv4AWp13fyXkEAEVAnPQ9dizV5ZXYz3DmHjYsR 70gOq6kGzHZIKp4lVQVBZLo5ukW86x8alJkwe8TPErGj3BSi1ukicyT0A1ZwzzWGD4lj xNmR2QsvX7DTqnJQvB2LkUjlC3zm/halE3zBkasnW5OTv/GWv1UEkcGZcyk9iCwf66DV GyNE0KwWtMfFy9o61TddlLYvwH/fn4kvtnRqu6axlmkKiwsyTZX0b+xmixIduXifekVB ICSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=lKXhSTCbXccG5no0exnIGvglSUDdtPd/dsPV2CUQhY7yNnjiltiEoN+b+lmNDRJAfh ixAh91pnR7gkOgzLvbL54Z3X/Ohnvhsb7VX88KpLrekywaQOG8wZG2BNHDtjmxNFQkm/ uORcnXbjMpMXGTpEePLLMWVmmNcG3IZcZKp4qC5Wi/zAMnAaidciye8NnXxsoF0XtFxT AACNKvXA4frlegp3B68iI1XbxNn4AHcMZgxaQyH65p5vB8uSWF9JxIj2DgG5NKOOPQq8 Lc7JV96dykNDnR4rfz7TB/zZDrerjnbqtQ3ndfDRN+6BfuBNWd967KQg1wz+hBx94sHD SeAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z9Rhg57g; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d7si1196955ejb.73.2020.12.03.06.23.19; Thu, 03 Dec 2020 06:23:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z9Rhg57g; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728814AbgLCOVx (ORCPT + 15 others); Thu, 3 Dec 2020 09:21:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbgLCOVx (ORCPT ); Thu, 3 Dec 2020 09:21:53 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6671AC061A51 for ; Thu, 3 Dec 2020 06:21:12 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id j205so2953350lfj.6 for ; Thu, 03 Dec 2020 06:21:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=Z9Rhg57g1DCSc0KWSEzs5Wt7vqrE+dqRvw1SDOx7OeWPYDwUhpqWJ/LvEEYRloQ3P9 XrfguVhNYmcRz/tXD8mzhWTso2hzMWmG2KYxN3I7xmx12myGplRet1CW4GO8UUmxYk+p vn3+k6bgAJyK4xi5kWJIOePqoMbXPXLopxVRp9pQXbRpyjn3ASoBfpfW6yAJYKk6gCYq 8UAfqvGTzotTY9jcgsBOB2VZ6eIRzrHx6NhJbux6o+LaQt2nxnRsdYFE6zuqPy8plaug +x6qTmOM6onFHFmsDI/1uami3AkZnwIh+QyC9MqtRa2D7dEdA31Zd0Gb+Ux6U/DjJBaW aW7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=ePUuM06aRBTPCg2Fox6SoTviRdjCibyOdYYTQPx09sqyUhu87KXhYKwKJUeD5mujau AaXoZsacmSv7qZrTCTWskBRkMTMin4l9/mMp2rec/0CM1F7JQuR/2rgaY6cZuVetLpzz vZoXZKC1uJGmGKtcpxyvjCGg+e2ysA2ENvlJjJOwY/2LxauxwmbWyOsyupKkniAqTLq3 seGf2sQeDLmXcnZaxcrDLe1WtuLAqPaaKqvzwuQY+Au+deSp08p7kKqSX6heXf7f4e9v nnrg/3CE7Zk/Hi2OWuXuhB5akd9NiCPU4j4EaIw2IARr0VmgkBjpc0dwvYdnJC6DvIgz tRtw== X-Gm-Message-State: AOAM531DdyuUUNDwnHgebLTERVzuTyYUVjmfMnP/PuUMQX6mCWygMwhm MyW4qrytqQH0YFFPhOEBx/0aZg== X-Received: by 2002:a19:c94:: with SMTP id 142mr1445563lfm.284.1607005270838; Thu, 03 Dec 2020 06:21:10 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.117]) by smtp.gmail.com with ESMTPSA id k185sm575716lfd.294.2020.12.03.06.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 06:21:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Date: Thu, 3 Dec 2020 17:20:59 +0300 Message-Id: <20201203142105.841666-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> References: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree nodes for mdss, mdp, dsi0/1. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 302 ++++++++++++++++++++++++++- 1 file changed, 295 insertions(+), 7 deletions(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..f4cae2b82e2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 { }; gpu: gpu@3d00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ compatible = "qcom,adreno-650.2", - "qcom,adreno", - "amd,imageon"; + "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; @@ -1803,6 +1799,298 @@ usb_2_dwc3: dwc3@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, + <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <460000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8250-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "dptx2_phy_pll_link_clk", + "dptx2_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;