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[23.128.96.18]) by mx.google.com with ESMTP id h13si1373293eja.245.2021.02.04.15.30.09; Thu, 04 Feb 2021 15:30:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NcUVBJ4Q; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230120AbhBDX3L (ORCPT + 16 others); Thu, 4 Feb 2021 18:29:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229500AbhBDX3F (ORCPT ); Thu, 4 Feb 2021 18:29:05 -0500 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04DE5C06178C for ; Thu, 4 Feb 2021 15:28:25 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id l12so5562499ljc.3 for ; Thu, 04 Feb 2021 15:28:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sDtJL1PbqVWXnwq2JOyelcfSEkHlszqUyvF72mpd46U=; b=NcUVBJ4QJGRr9ul/MdwBMNOcLVmxW19+bh2uGmxKkMw/Ag7bP6Thigw/pSAo3rvQRP GQIWMNT0ULKp9q8Ub1LeUBDd7Xu/fi2KalCyzP1W7z1OGRi67feE3nclgrneFyzAyb0m luOC15aEC4MDf4w8TNqwPMlGBH01KSM+Uf4sBWhG/qvINMEhhelao2pVNohdMFWntmi4 nuT5cYyIgV75iJwEKFWIcg74+KAIqvEusfDXKLD2XZBg4fa/CFmENtFtBNJltDJpT0rb mGujSD8FjHU9bITlKHTyVBkl7BA5s8/YAx7isBuZzcUILolArfixwnYh+mNK7OyJoiK0 9ZJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sDtJL1PbqVWXnwq2JOyelcfSEkHlszqUyvF72mpd46U=; b=fAVALIxcscJ8ZU4ijlsNEkq9nDBhOz4Vvoc/GykTHRCtAmeomvk0SjrIuP9cMAn7Xe +gRZYn5VmNiSxNuEqRfxUr+RtiWK5XBWihu01SiiS+yoUulDSy+sZvoMP6bos4SnF1kt Y2JbGPY9rbTvU3liLZuH3AAw071Y9fEBj/ymQMu5CTnxQLvytZ4DpXBzQchrF/4Unomy XXd7LWEtsTplooQxsKEG+5sVTll2iDEKs1hhsZ527G6DWG87WLhxGwUe7jH3JzD/Sd4Z 7MwXbplr5qVkDUiDpwhLCgmqA4y5bHRHs8+OuONFCfb2zVytStQQ5syLlkE6xJnbmaDO EDYQ== X-Gm-Message-State: AOAM530XFBR+ffglCW+IAcytER39993F9VBN+nfeHDtTzQJxE9Vl0tS/ A3tTLfRz8l6AoQmFWWHXXS71qIMN6dXmX0Uj X-Received: by 2002:a2e:300d:: with SMTP id w13mr957734ljw.383.1612481303516; Thu, 04 Feb 2021 15:28:23 -0800 (PST) Received: from eriador.lan ([188.162.64.67]) by smtp.gmail.com with ESMTPSA id x20sm769906lfe.256.2021.02.04.15.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Feb 2021 15:28:23 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jishnu Prakash , Rob Herring Subject: [PATCH v13 1/2] dt-bindings: thermal: qcom: add adc-thermal monitor bindings Date: Fri, 5 Feb 2021 02:28:08 +0300 Message-Id: <20210204232809.474733-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210204232809.474733-1-dmitry.baryshkov@linaro.org> References: <20210204232809.474733-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for thermal monitor, part of Qualcomm PMIC5 chips. It is a close counterpart of VADC part of those PMICs. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 153 ++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml -- 2.30.0 diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml new file mode 100644 index 000000000000..7cd364430573 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC Thermal Monitoring +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + const: qcom,spmi-adc-tm5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of samples to be used for measurement. + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + default: 1 + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: + - 250 + - 420 + - 840 + default: 840 + +patternProperties: + "^([-a-z0-9]*)@[0-7]$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM + minimum: 0 + maximum: 7 + + io-channels: + description: + From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor + + qcom,ratiometric: + $ref: /schemas/types.yaml#/definitions/flag + description: + Channel calibration type. + If this property is specified VADC will use the VDD reference + (1.875V) and GND for channel calibration. If property is not found, + channel will be calibrated with 0V and 1.25V reference channels, + also known as absolute calibration. + + qcom,hw-settle-time-us: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Time between AMUX getting configured and the ADC starting conversion. + enum: [15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000] + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Used for scaling the channel input signal before the + signal is fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by + which input signal is multiplied. For example, <1 3> indicates the + signal is scaled down to 1/3 of its value before ADC measurement. If + property is not found default value depending on chip will be used. + items: + - const: 1 + - enum: [ 1, 3, 4, 6, 20, 8, 10 ] + + required: + - reg + - io-channels + + additionalProperties: + false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + pm8150b_adc: adc@3100 { + reg = <0x3100>; + compatible = "qcom,spmi-adc5"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* Other propreties are omitted */ + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + }; + }; +...