From patchwork Thu Jun 17 22:20:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 462205 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp887176jae; Thu, 17 Jun 2021 15:20:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyY6dCCXmFW0jRGXARlaSrIymbicBi0GdJDOmlqYYssk68AJpWtZ5nYeKjxfbdmGS1QWorn X-Received: by 2002:a6b:6b11:: with SMTP id g17mr5804660ioc.101.1623968437732; Thu, 17 Jun 2021 15:20:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623968437; cv=none; d=google.com; s=arc-20160816; b=FSaWCYwHqTsSy6CQjoAk1B57nlT5UFpOSqpubr96kL7RYRPlvXHqZXkJB/1xRCt407 0t73nSzZo9RiuoP9C8fvXNQRpkl/w6Ms0yrnknR8I2Z2LcF6riCSETHm7L6NzWb924cn XZbAhfCFX/ENV3FBCQn6l5GFrRlUlE3r0nwdbzeMHOy5tbNNZtVcyFsTh9HifxB2rY8f tp7i0N9/Uv2caYeFDVeleb6UIkBMnRpVmh2FbpFtB/75nOkEcIAWTZJWQf3f2PGLvOyX nOsfcaP5geJf3wH5zsuVyobru3QF3s8sIFp1OWqxyUAubS2urI3IQ062rK8OueCcFFPW XRcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9Jzs2DywkTXblufGfcJJvXwLGtRDUMYYgqcQdK2UvYs=; b=emRZ3QRXUO2h9SPPufdGOZFiKzZkNhJaq6lKFAKYfMQiy1gVLifvdOGaVsf6ViRhzx 7guFS9zKjo7QnTMFmzeyGL93+mP6ZHwR4kgzUtmmKfgWZTNGlPLW/A0Hq/LdoYhqbMPs GmgqPO7YI4Wx5Aq2IjgaXn6KuvCp8jt95Rfzye8GVLPjqTKV60KL3cSbwzRUYrWMO0M/ cjpxke+UuAE0SADS01yD1FvagwyEFx1juIjbB+aQQxDN2Ncovau+/LItygkbrinQr4nt F9+nMaYowgRI3nRNUb8/G/mU17aaVc5iXgSn1TkWC+jNsBNNpqarm/VZIU12Yk8XdtOT hmqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nf/R3gMK"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i26si6444195iol.73.2021.06.17.15.20.37; Thu, 17 Jun 2021 15:20:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nf/R3gMK"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231896AbhFQWWo (ORCPT + 17 others); Thu, 17 Jun 2021 18:22:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231250AbhFQWWo (ORCPT ); Thu, 17 Jun 2021 18:22:44 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21A87C06175F for ; Thu, 17 Jun 2021 15:20:35 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id 131so11221209ljj.3 for ; Thu, 17 Jun 2021 15:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Jzs2DywkTXblufGfcJJvXwLGtRDUMYYgqcQdK2UvYs=; b=nf/R3gMKmZ8YgJAIeW60PBX9O9+j3CsjOZDroP9lA9yyvHNR7Ca40xUawrTgWUTg1N BQu0Z5+/n5ovKf0/qjnQ7GG9EOwTdpb2mGE2O4V+w6lbeZ3wt1rw6R/bBn8NyWydIsSD S1NKDTJSygtKDGiQsk1U2BbPWwHLQUwjjKjMict3x1ahfh8Br1AviN9pzzeGsLdH8Scm TesUzsO8PJxSSWSsizW9MeGAwk01dFj8tC29SB2w7R857fqIpzcfS6YJs6AyCc6d31ge vP4uqGgoxapXtXrsDxq6P6IlvhEgkbaNgFCAkkflnpqORETZ5Xltds3q89BC+TV2slmH nnSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Jzs2DywkTXblufGfcJJvXwLGtRDUMYYgqcQdK2UvYs=; b=WSt0+5BlOGhyHw+N1ZX3SBWA9Yl8b19vSWvNQS/GGBEqDoHgF/W8qyM3i2uYTjYIJQ YpChjJz+2vM/c5cG5Knm6fv2eKE7fX0k0rm7ur+qY6jXiFQi0kCUusCfUY8gAh5JJ9Cv FxAS89TNe513fh92xiWEbr7H4K48NefIiZDagJqGapgxpi/3Tq1I1SSVM1wEjNj3SuK6 +IpIoAmR9Tsvk4cne3ZhEJfNkOYGU5U7YPo3e0j8jmhGDvAeBtl3IkCjKhVNz9gvrw86 EqmIw+GIyYlA1ldBtcJTmTyh0EUkUcCiJ+zHxqKdFTA48j6/B3+S72dDW2Iqf2G8j6to Mpgw== X-Gm-Message-State: AOAM5311YD6ov/rBcV7jKjd8+aA/TbmDQzQw20cOK/Lr6ge19JoYL24a 3TfGW2EmBHqF9uYCXPih1vIXsA== X-Received: by 2002:a2e:9f14:: with SMTP id u20mr1035864ljk.222.1623968433429; Thu, 17 Jun 2021 15:20:33 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id a5sm895594ljq.0.2021.06.17.15.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jun 2021 15:20:32 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 2/7] drm/msm/dpu: don't clear IRQ register twice Date: Fri, 18 Jun 2021 01:20:24 +0300 Message-Id: <20210617222029.463045-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210617222029.463045-1-dmitry.baryshkov@linaro.org> References: <20210617222029.463045-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We already clear the IRQ status register before processing IRQs, so do not clear the register again. Especially do not clear the IRQ status _after_ processing the IRQ as this way we can loose the event. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 17 ----------------- 1 file changed, 17 deletions(-) -- 2.30.2 Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 2437b0c7c073..28e9b0d448db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = { #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) #define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32)) -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, - int irq_idx) -{ - int reg_idx; - - if (!intr) - return; - - reg_idx = DPU_IRQ_REG(irq_idx); - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx)); - - /* ensure register writes go through */ - wmb(); -} - /** * dpu_core_irq_callback_handler - dispatch core interrupts * @arg: private data of callback handler @@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) dpu_core_irq_callback_handler(dpu_kms, irq_idx); - dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); - /* * When callback finish, clear the irq_status * with the matching mask. Once irq_status