From patchwork Thu Jul 15 06:51:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 477402 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1408818jao; Wed, 14 Jul 2021 23:52:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvBwSqw9nSsFqS8nY/OPUXTpF8PMggo4HH/qIJyry5IIf7XP4hVISujL+rWKr5gYSGMQco X-Received: by 2002:a05:6402:30af:: with SMTP id df15mr4579469edb.19.1626331969142; Wed, 14 Jul 2021 23:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626331969; cv=none; d=google.com; s=arc-20160816; b=XoM+VKASNmFp5Kl/Hj+BwNCVNq8VbbS4G6bHTkeklTrbRwkjZAX79T6qRX+6BzOuoW UmR56yBeltod3NHzuc2Ot96P77wL3sZ+B4URwBWBhzDWBh6dzsLnjoEpEDsxVbvxVnF1 kHDlow+QLIrV7wYSt5yI+TuzjvtTN0qfETM4YPAfSYkzWayFG4TXZF4v13btsUUZfn25 OxrrcqS1eylj2Tf6g5j5mW5oZycApI5TUKEbHcoXlLEd+QS+goV1+1KU6//N3mn72OQV xY8AfCO0tNdaKdA83T6NFD52L2GecIivs1acfoumXdEPFkDvnhaBGefXAVXVkNhkGS/k J1JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VemsNs5HgqWw6zuK5JpHZAoUeI+o9KTXaz3S1W/FrjU=; b=RkecQ9oDL8g6ezBkx17vYt4iIUTEOXrQCkQphwsJOa9FY2Zgma8bp3z0rT6Dcb0/hc cwjURYJq+ORGcqKDfEYobvfZ3vhWIS9ryIZJc6lGMZl0PxSIhOSmg90zm7wMN5O5MxY3 jGrRw4swqiSCJOXUrleoLQK41yckJoo3gndjt1bBdHSh/UdhlpX9f6CWYiXgQfCs1d/e 98O7U1PUfGM94+fq1LUWH+8297HjArqvTZ4twYEPyPlEc3SnroK1+UMQIojYxnV8RDau z0/THWStRxRuaGwAk5ZBmPgqGy1GO46Xc/Qwa0HeXDGR+2CSdhnufAdUbS3fJWJDP3rx kcSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=gsEjiu1n; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Thu, 15 Jul 2021 06:52:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626331965; bh=a+mNFMjjqFt7dXv9hTeS3+zdFKT2pg+Uw0o4LY2Z9ms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gsEjiu1n+fyR6iWMpO+7KZPudHghrzZ5QozxUfn6sPwrHuzCrKmsQcziECySKZrkK VFPh9bGqMElNu6dzSANRqEoiEn8V28NJmvFv2EeOHRqrqlY90azgKZQQr16XV8yWjK FqWpi7tJSqwpglW1uOtt6CC5IizzqoNSpUXDtn7Y0GbMXsvlgPHvZukvT3e7mudv+S pEDpiaoiJ8DG7Kq+uN0J8ts2dLacfUU+KjVUMOUpZru/m8FMOxfHrdzdgqBkvYC0Np deM2fPwaqlCJyFf7fA35eGkUAIJoYczU6+sek8qbQkWpof9lqLsB480P1tvhP4A88A 9nv1HbOFS/i9g== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , Jeffrey Hugo , Sumit Semwal , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 04/11] drm/msm/disp/dpu1: Add DSC support in RM Date: Thu, 15 Jul 2021 12:21:56 +0530 Message-Id: <20210715065203.709914-5-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715065203.709914-1-vkoul@kernel.org> References: <20210715065203.709914-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add the bits in RM to enable the DSC blocks Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + 3 files changed, 34 insertions(+) -- 2.31.1 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d6717d6672f7..d56c05146dfe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -165,6 +165,7 @@ struct dpu_global_state { uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index fd2d104f0a91..4da6d72b7996 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -11,6 +11,7 @@ #include "dpu_hw_intf.h" #include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" +#include "dpu_hw_dsc.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_intf_destroy(hw); } } + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) { + struct dpu_hw_dsc *hw; + + if (rm->intf_blks[i]) { + hw = to_dpu_hw_dsc(rm->dsc_blks[i]); + dpu_hw_dsc_destroy(hw); + } + } return 0; } @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; } + for (i = 0; i < cat->dsc_count; i++) { + struct dpu_hw_dsc *hw; + const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; + + hw = dpu_hw_dsc_init(dsc->id, mmio, cat); + if (IS_ERR_OR_NULL(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed dsc object creation: err %d\n", rc); + goto fail; + } + rm->dsc_blks[dsc->id - DSC_0] = &hw->base; + } + return 0; fail: @@ -476,6 +498,9 @@ static int _dpu_rm_reserve_intf( } global_state->intf_to_enc_id[idx] = enc_id; + + global_state->dsc_to_enc_id[0] = enc_id; + global_state->dsc_to_enc_id[1] = enc_id; return 0; } @@ -567,6 +592,8 @@ void dpu_rm_release(struct dpu_global_state *global_state, ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->intf_to_enc_id, ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id); + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); } int dpu_rm_reserve( @@ -640,6 +667,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->dspp_to_enc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break; + case DPU_HW_BLK_DSC: + hw_blks = rm->dsc_blks; + hw_to_enc_id = global_state->dsc_to_enc_id; + max_blks = ARRAY_SIZE(rm->dsc_blks); + break; default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..278d2a510b80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -30,6 +30,7 @@ struct dpu_rm { struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; uint32_t lm_max_width; };