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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id r2sm3691694wmq.24.2022.02.17.15.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Feb 2022 15:57:08 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/16] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Date: Fri, 18 Feb 2022 00:56:53 +0100 Message-Id: <20220217235703.26641-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220217235703.26641-1-ansuelsmth@gmail.com> References: <20220217235703.26641-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 828383c30322..f6db7247835e 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, },