From patchwork Thu Jul 14 12:34:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 590958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 768CCCCA486 for ; Thu, 14 Jul 2022 12:34:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239323AbiGNMeW (ORCPT ); Thu, 14 Jul 2022 08:34:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239325AbiGNMeV (ORCPT ); Thu, 14 Jul 2022 08:34:21 -0400 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [5.144.164.169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D0175C369 for ; Thu, 14 Jul 2022 05:34:18 -0700 (PDT) Received: from localhost.localdomain (abxj14.neoplus.adsl.tpnet.pl [83.9.3.14]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 7FF9A3F5E3; Thu, 14 Jul 2022 14:34:15 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: qcom: sm8450: Add SDHCI2 Date: Thu, 14 Jul 2022 14:34:05 +0200 Message-Id: <20220714123406.1919836-4-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220714123406.1919836-1-konrad.dybcio@somainline.org> References: <20220714123406.1919836-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and configure the SDHCI host responsible for (mostly) SD Card and its corresponding pins' sleep states. Signed-off-by: Konrad Dybcio --- Changes since v1: - change the opp table's node name to 'opp-table' arch/arm64/boot/dts/qcom/sm8450.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 09e7587de0de..29389fcfa99b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2355,6 +2355,26 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + sdc2_sleep_state: sdc2-sleep { + clk { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie0_default_state: pcie0-default-state { perst { pins = "gpio94"; @@ -3101,6 +3121,45 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4a0 0x0>; + power-domains = <&rpmhpd SM8450_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>;