From patchwork Wed Aug 31 18:58:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 601483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20E9CC65C0D for ; Wed, 31 Aug 2022 18:59:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229735AbiHaS7n (ORCPT ); Wed, 31 Aug 2022 14:59:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233155AbiHaS7g (ORCPT ); Wed, 31 Aug 2022 14:59:36 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53A69BD1FC for ; Wed, 31 Aug 2022 11:58:37 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id q16so15576663ljp.8 for ; Wed, 31 Aug 2022 11:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=WQg7blSGne2/YmKGXSUdX/PkxQiySd7D40Q+frbabYM=; b=AsO0AdxmoBVbdXdtwrUgQTDRuruty4QoMO4z/L4tD04B0fo5gfzg/sKUSRULgKnz8P IfBeYkicjC+FMl8rXkyLUY3FpKyg+ZLlZU1M4otna+D0yx86LrMq54N3Ofbxp9GMVgi3 TeNRaRje6NdBGTWhnWzIgFA1dOEE5eaB46hGkqNzZz6DRBXqQok5hTWZqHER2xuB/hlv 1DaBnnhq6aRakyhFwqy8aQMhB6F9+06AbMjQpIb6UiMALf3bRpekBBJJCPje2PHS6OTy n1kRuY3pUO0+nucKibhSj5uaHPbrXFdy0V5sG2f6RGeo6nyjYxmbPdP4t5qdvF70LoVa 7Epg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=WQg7blSGne2/YmKGXSUdX/PkxQiySd7D40Q+frbabYM=; b=bMXglR6KETISOVU1CvjldCVzZMjdkPXPZL4ZOddm7WuRGdOoEagOvhdVAZfhJ79bAU 4FGJRN3Yj+7FVLFT30NEY3p6bqtUxHoxbLUSRn6uxFUJIJMmXnB5Y5ek48aG7u8MU95e BPLav+Zq6toxEkHUb1aE1zfXX60NFs1mADppI3UAhEqSSNhLRwbh2f/iRJE92pzF1o71 qfv9zDrLs3PSVO1tAmN4HlUqJZVRfq07o0YF8TWKhRAjLp1ScgwtSAm1KG+dSiPEpHAi nnbxIMWSWNWiO/i3bNn4EgbC9MwH7SDUfevKDpunNfBaxQrfbGWDZX9dCUWPyRnHPMyM OouQ== X-Gm-Message-State: ACgBeo1/Ga0snZNMI4sL8z8h58cUUkzssHpp5hTyWtPEkbOdT0iOupYp Lqf9mY0sFxJ0gEZk+ae8As0mYw== X-Google-Smtp-Source: AA6agR4BPwTnYvWLcSvyogov3vEWYpBlUq47kQkLejcjh+02MMGXLMANJJs82qpTi2lRmQot5Mm8rQ== X-Received: by 2002:a2e:bd8b:0:b0:264:8256:c23f with SMTP id o11-20020a2ebd8b000000b002648256c23fmr4945603ljq.508.1661972315607; Wed, 31 Aug 2022 11:58:35 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g1-20020a0565123b8100b004948f583e6bsm322422lfv.138.2022.08.31.11.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 11:58:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , Loic Poulain Subject: [PATCH v5 05/12] dt-bindings: display/msm: move common MDSS properties to mdss-common.yaml Date: Wed, 31 Aug 2022 21:58:23 +0300 Message-Id: <20220831185830.1798676-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220831185830.1798676-1-dmitry.baryshkov@linaro.org> References: <20220831185830.1798676-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move properties common to all MDSS DT nodes to the mdss-common.yaml. This extends qcom,msm8998-mdss schema to allow interconnect nodes, which will be added later, once msm8998 gains interconnect support. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-msm8998.yaml | 42 ++-------- .../bindings/display/msm/dpu-qcm2290.yaml | 52 ++---------- .../bindings/display/msm/dpu-sc7180.yaml | 51 ++---------- .../bindings/display/msm/dpu-sc7280.yaml | 51 ++---------- .../bindings/display/msm/dpu-sdm845.yaml | 55 ++---------- .../bindings/display/msm/mdss-common.yaml | 83 +++++++++++++++++++ 6 files changed, 116 insertions(+), 218 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-common.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 0d6743eabd27..1e6b7e15f1c5 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -14,20 +14,14 @@ description: | sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for MSM8998 target. +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,msm8998-mdss - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - clocks: items: - description: Display AHB clock @@ -40,23 +34,8 @@ properties: - const: bus - const: core - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -102,18 +81,7 @@ patternProperties: - const: core - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index bec3c131c0dc..1c6dd7969a61 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -14,20 +14,14 @@ description: | sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS and DPU are mentioned for QCM2290 target. +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,qcm2290-mdss - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - clocks: items: - description: Display AHB clock from gcc @@ -40,35 +34,14 @@ properties: - const: bus - const: core - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true + maxItems: 2 interconnects: - items: - - description: Interconnect path specifying the port ids for data bus + maxItems: 1 interconnect-names: - const: mdp0-mem - - resets: - items: - - description: MDSS_CORE reset + maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -110,18 +83,7 @@ patternProperties: - const: lut - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index 732b9d8f968a..47e74f78e939 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -14,20 +14,14 @@ description: | sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for SC7180 target. +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,sc7180-mdss - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - clocks: items: - description: Display AHB clock from gcc @@ -40,34 +34,14 @@ properties: - const: ahb - const: core - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + maxItems: 1 interconnects: - items: - - description: Interconnect path specifying the port ids for data bus + maxItems: 1 interconnect-names: - const: mdp0-mem - - resets: - items: - - description: MDSS_CORE reset + maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -111,18 +85,7 @@ patternProperties: - const: core - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index 4889129660c6..7dc624a26e2e 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -14,19 +14,13 @@ description: | sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for SC7280. +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: const: qcom,sc7280-mdss - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - clocks: items: - description: Display AHB clock from gcc @@ -39,34 +33,14 @@ properties: - const: ahb - const: core - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + maxItems: 1 interconnects: - items: - - description: Interconnect path specifying the port ids for data bus + maxItems: 1 interconnect-names: - const: mdp0-mem - - resets: - items: - - description: MDSS_CORE reset + maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -109,18 +83,7 @@ patternProperties: - const: core - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index b275f928a921..7e9d7c7f3538 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -14,20 +14,14 @@ description: | sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for SDM845 target. +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,sdm845-mdss - reg: - maxItems: 1 - - reg-names: - const: mdss - - power-domains: - maxItems: 1 - clocks: items: - description: Display AHB clock from gcc @@ -38,38 +32,14 @@ properties: - const: iface - const: core - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true + maxItems: 2 interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - description: Interconnect path specifying the port ids for data bus + maxItems: 2 interconnect-names: - items: - - const: mdp0-mem - - const: mdp1-mem - - resets: - items: - - description: MDSS_CORE reset + maxItems: 2 patternProperties: "^display-controller@[0-9a-f]+$": @@ -111,18 +81,7 @@ patternProperties: - const: core - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml new file mode 100644 index 000000000000..053c1e889552 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display MDSS dt properties (common properties) + +maintainers: + - Krishna Manikandan + - Dmitry Baryshkov + - Rob Clark + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. + +properties: + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + minItems: 1 + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + + ranges: true + + interconnects: + minItems: 1 + items: + - description: Interconnect path specifying the port ids for data bus + - description: Interconnect path specifying the port ids for data bus + + interconnect-names: + minItems: 1 + items: + - const: mdp0-mem + - const: mdp1-mem + + resets: + items: + - description: MDSS_CORE reset + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: true