From patchwork Wed Oct 5 09:07:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 612577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8423DC43217 for ; Wed, 5 Oct 2022 09:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230194AbiJEJIx (ORCPT ); Wed, 5 Oct 2022 05:08:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230218AbiJEJIk (ORCPT ); Wed, 5 Oct 2022 05:08:40 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76FFE76978; Wed, 5 Oct 2022 02:08:13 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2958upN5021784; Wed, 5 Oct 2022 09:08:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=zOz9DK0Yg3l8J1gu2rZxNW57wndut0TuBanZP/1eDxQ=; b=gFloYDbF4iF5l5qYWZrqFTPuuD9JEjrlf/8a3JJjMB3jVSZ1xH/Kfr55WPAQWuc1NqAl aabs7b6VEQC2LVdEhsUDLmS5ULytHcovVfcjcmcBtD+vY7Sg2Xv16PttaPQKNYuVVYMF qEKn/PwX/I/OktiUTdbjb2Fkp1As0GTwCtcbAOvXHVW//1t1+EwBebHAhgi6kBQKUB78 1wJ3sVU8WPX1mzdTg/tX0jV2twVPn3Ww1mtIMO9lI6k8w/6u5z8RU69JT9URsdiona8J 2AAnXY0FcIAf4KD6Gt/qjw7G0v+PM6LrizGQSTtKvq5qo4TFadpZbzXASS999BcV8Fm0 IQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k06sjkrkx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:08:03 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 295982tX021829 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:08:02 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:57 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH v7 6/6] arm64: dts: qcom: sc7280: Add Reset support for gpu Date: Wed, 5 Oct 2022 14:37:04 +0530 Message-ID: <20221005143618.v7.6.I6a1fca5d53c886c05ea3e24cd4282d31c9c0cd0b@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Mav_tV04SwmxJ7L7HRA0Hy4wXhJxxjxB X-Proofpoint-GUID: Mav_tV04SwmxJ7L7HRA0Hy4wXhJxxjxB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Reset using GPUCC driver for GPU. This helps to ensure that GPU state is reset by making sure that CX head switch is collapsed. Signed-off-by: Akhil P Oommen --- (no changes since v1) arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 2125803..3e559b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2535,6 +2535,9 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + resets = <&gpucc GPU_CX_COLLAPSE>; + reset-names = "cx_collapse"; + gpu_opp_table: opp-table { compatible = "operating-points-v2";