From patchwork Tue Oct 25 07:32:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 618202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D09C04A95 for ; Tue, 25 Oct 2022 07:33:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231867AbiJYHdn (ORCPT ); Tue, 25 Oct 2022 03:33:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229685AbiJYHdW (ORCPT ); Tue, 25 Oct 2022 03:33:22 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DF3AEC1CE for ; Tue, 25 Oct 2022 00:33:19 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id u6so10457606plq.12 for ; Tue, 25 Oct 2022 00:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5vgVZXeinbhpnwzOcj3FGms9cM/M5Xj4R/cDa4Tk1cA=; b=TGd3emrQMlbojhGNu0dbqI9EDiqhKWR1EA1BCRn6M1s0Ek+26HO48OcJlHPHVt1fE9 /Aof45ri7isiNPBEN9JrAKWNGaZPm1qNpcskltAHsisRPHwXMy8eI2R4LZYvs7d6FDwU mdxHVABURTLM+5KDPFAA+dMpJekVIKOgZziKX0BbgHdcYRGJdv9CvQjwe8COtGS+HnEy YMtph4uwAirSrVctzXmQMvt3Y8g+C1S4DXDGHU6nL24itBj6yl4X5wbQV67StBJyCEFZ 003KeZIPHSs1WfdXw+9qmZh10uaAAkgqPtq58A+4czxUR769AqDbvnRSyF4dWzhu2CU7 xCEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5vgVZXeinbhpnwzOcj3FGms9cM/M5Xj4R/cDa4Tk1cA=; b=GvWIJ4r1AcpGZ8IDuSYp3BN9qM7uTWlM1xSBjLPdTYtSg85WyWVSxnqZdgNt0YY6zD bNieAAeJ/S1y4gHxVjLLGaiQ1O0n6WgQLaYq5JUwsLY2WkvSW5pMUF0CWlc4w3E4OBwA tBCcCY/qTSUdTS1dRtSR4nNVd0Zgjdo4beKYUSUMoZJG3shLPCflIwwAjAFBnJ6UXpTi gHXeiToxQ6RxKTSYjkxEUAjSk0kcfaDuvbn9IsdzHxSeCkL2KntKYzhg8Nuxth5szY3R EsoCAQ8C1BtsLqOb4JRxjkt6Meao9dUjUZZPCaObzwVAj+Fj5ZKwJuJb4bIw1BRDdlMU IxLQ== X-Gm-Message-State: ACrzQf17hXDR6vY/0eHjMm9NZhug5F8Pzz6KejbN8JjRaHuoRq3cerK2 E+QXPNijDwsBpISJEujrMAkdkyxUxpx9t2IdVg== X-Google-Smtp-Source: AMsMyM4/P/QQnBjfl6VcKyYKrffX4U63x2omE5TKgDTUDBnLXh9PuJH/wMTl1tjNWqSO5bD9SeA/6g== X-Received: by 2002:a17:90b:4a84:b0:20d:8953:5ab0 with SMTP id lp4-20020a17090b4a8400b0020d89535ab0mr78384541pjb.48.1666683199432; Tue, 25 Oct 2022 00:33:19 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:17 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 2/7] arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs Date: Tue, 25 Oct 2022 13:02:49 +0530 Message-Id: <20221025073254.1564622-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6c18cfca9a34..8f26cf9aad01 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -52,6 +52,7 @@ CPU0: cpu@0 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -71,6 +72,7 @@ CPU1: cpu@100 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -87,6 +89,7 @@ CPU2: cpu@200 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +106,7 @@ CPU3: cpu@300 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -119,6 +123,7 @@ CPU4: cpu@400 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -135,6 +140,7 @@ CPU5: cpu@500 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +158,7 @@ CPU6: cpu@600 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -168,6 +175,7 @@ CPU7: cpu@700 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -3804,6 +3812,7 @@ cpufreq_hw: cpufreq@17d91000 { ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; gem_noc: interconnect@19100000 {