From patchwork Fri Nov 11 13:55:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 625768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA8F1C4167E for ; Fri, 11 Nov 2022 13:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234100AbiKKN7N (ORCPT ); Fri, 11 Nov 2022 08:59:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234104AbiKKN6u (ORCPT ); Fri, 11 Nov 2022 08:58:50 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3357657DE; Fri, 11 Nov 2022 05:55:40 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C60566602A3F; Fri, 11 Nov 2022 13:55:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668174939; bh=UBkv+ig7/g4aGwYjmkedbumqTxGbFTwuxpKvSYfzEUY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mnYXIgjbhdmAMH95SV4rvYPVvcfa4VDDDNGgZgdldCv1h31RsIztMeFx0uvDzqG6y sZJfSQIQ3pJz+C88Req3R/NTVepKxxeDzSqH3LXJl/6IluGNxLWsoc2SFC8U2wDb7X RLXXSZKQ+HKlcSSKdF8JhOX8EKd0WvR5RT2aCtPb3qzxDOSt+xYCPFtO+fNqoL9Jp2 xy8AGxV7Dz6/j79ZIx9nVvLDg1C3cnvtEmp2EYF05mvJFaPp10OV/PBzyrq33kn1XK dz3zpvD1zGbvxtAuuBiO0ALreLdYyJDyS1u49gm721iQNiS8tdslg14a1JfQvZdIeQ rutX8glEqTBJw== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robdclark@gmail.com, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH 2/7] iommu/qcom: Use the asid read from device-tree if specified Date: Fri, 11 Nov 2022 14:55:20 +0100 Message-Id: <20221111135525.204134-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111135525.204134-1-angelogioacchino.delregno@collabora.com> References: <20221111135525.204134-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As specified in this driver, the context banks are 0x1000 apart but on some SoCs the context number does not necessarily match this logic, hence we end up using the wrong ASID: keeping in mind that this IOMMU implementation relies heavily on SCM (TZ) calls, it is mandatory that we communicate the right context number. Since this is all about how context banks are mapped in firmware, which may be board dependent (as a different firmware version may eventually change the expected context bank numbers), introduce a new property "qcom,ctx-num": when found, the ASID will be forced as read from the devicetree. When "qcom,ctx-num" is not found, this driver retains the previous behavior as to avoid breaking older devicetrees or systems that do not require forcing ASID numbers. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index bfd7b51eb5db..491a8093f3d6 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -551,7 +551,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) * index into qcom_iommu->ctxs: */ if (WARN_ON(asid < 1) || - WARN_ON(asid > qcom_iommu->num_ctxs)) { + WARN_ON(asid > qcom_iommu->num_ctxs) || + WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) { put_device(&iommu_pdev->dev); return -EINVAL; } @@ -638,7 +639,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev) static int get_asid(const struct device_node *np) { - u32 reg; + u32 reg, val; + int asid; /* read the "reg" property directly to get the relative address * of the context bank, and calculate the asid from that: @@ -646,7 +648,17 @@ static int get_asid(const struct device_node *np) if (of_property_read_u32_index(np, "reg", 0, ®)) return -ENODEV; - return reg / 0x1000; /* context banks are 0x1000 apart */ + /* + * Context banks are 0x1000 apart but, in some cases, the ASID + * number doesn't match to this logic and needs to be passed + * from the DT configuration explicitly. + */ + if (of_property_read_u32(np, "qcom,ctx-num", &val)) + asid = reg / 0x1000; + else + asid = val; + + return asid; } static int qcom_iommu_ctx_probe(struct platform_device *pdev)