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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id s3-20020adfecc3000000b0022e653f5abbsm15459168wro.69.2022.11.16.08.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 08:28:13 -0800 (PST) From: Bryan O'Donoghue To: robert.foss@linaro.org, todor.too@gmail.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, mchehab@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dmitry.baryshkov@linaro.org, vladimir.zapolskiy@linaro.org Cc: sakari.ailus@iki.fi, hverkuil@xs4all.nl, laurent.pinchart@ideasonboard.com, quic_mmitkov@quicinc.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH v6 6/7] arm64: dts: qcom: sm8250: camss: Define ports and ports address/size cells Date: Wed, 16 Nov 2022 16:28:00 +0000 Message-Id: <20221116162801.546737-7-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221116162801.546737-1-bryan.odonoghue@linaro.org> References: <20221116162801.546737-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define the set of possible ports, one for each CSI PHY along with the port address and size cells @ the SoC dtsi level. Suggested-by: Konrad Dybcio Suggested-by: Laurent Pinchart Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d517d6a80bdcb..806aa19ad93ce 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3412,6 +3412,35 @@ camss: camss@ac6a000 { "cam_hf_0_mnoc", "cam_sf_0_mnoc", "cam_sf_icp_mnoc"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + }; + }; }; camcc: clock-controller@ad00000 {