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[83.30.148.110]) by smtp.gmail.com with ESMTPSA id a25-20020a056512201900b004b4e9580b1asm369754lfb.66.2022.11.30.12.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 12:10:02 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 03/12] arm64: dts: qcom: sm6115: Add cpufreq-hw support Date: Wed, 30 Nov 2022 21:09:41 +0100 Message-Id: <20221130200950.144618-4-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221130200950.144618-1-a39.skl@gmail.com> References: <20221130200950.144618-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 0340ed21be05..2a55087b103e 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -41,6 +41,7 @@ CPU0: cpu@0 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -55,6 +56,7 @@ CPU1: cpu@1 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU2: cpu@2 { @@ -65,6 +67,7 @@ CPU2: cpu@2 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU3: cpu@3 { @@ -75,6 +78,7 @@ CPU3: cpu@3 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU4: cpu@100 { @@ -85,6 +89,7 @@ CPU4: cpu@100 { capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -99,6 +104,7 @@ CPU5: cpu@101 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; CPU6: cpu@102 { @@ -109,6 +115,7 @@ CPU6: cpu@102 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; CPU7: cpu@103 { @@ -119,6 +126,7 @@ CPU7: cpu@103 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; cpu-map { @@ -842,6 +850,17 @@ intc: interrupt-controller@f200000 { redistributor-stride = <0x0 0x20000>; interrupts = ; }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; + + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer {