From patchwork Wed Dec 14 23:20:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 634567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E43A4C3DA6D for ; Wed, 14 Dec 2022 23:21:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229511AbiLNXVd (ORCPT ); Wed, 14 Dec 2022 18:21:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbiLNXVW (ORCPT ); Wed, 14 Dec 2022 18:21:22 -0500 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [5.144.164.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8572C770; Wed, 14 Dec 2022 15:21:18 -0800 (PST) Received: from localhost.localdomain (94-209-172-39.cable.dynamic.v4.ziggo.nl [94.209.172.39]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id E1B8F20395; Thu, 15 Dec 2022 00:21:16 +0100 (CET) From: Marijn Suijten To: phone-devel@vger.kernel.org, Bjorn Andersson Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Luca Weiss , Adam Skladowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] arm64: dts: qcom: msm8976: Declare and use SDC1 pins Date: Thu, 15 Dec 2022 00:20:47 +0100 Message-Id: <20221214232049.703484-5-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221214232049.703484-1-marijn.suijten@somainline.org> References: <20221214232049.703484-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the pinctrl states for SDC1 and use them on sdhc_1. Signed-off-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 05dcb30b0779..7d4c7548882c 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -508,6 +508,56 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; + sdc1_off_state: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_on_state: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + spi1_default: spi0-default-state { spi-pins { pins = "gpio0", "gpio1", "gpio3"; @@ -680,6 +730,11 @@ sdhc_1: mmc@7824000 { <&gcc GCC_SDCC1_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc1_on_state>; + pinctrl-1 = <&sdc1_off_state>; + pinctrl-names = "default", "sleep"; + status = "disabled"; };