Message ID | 20230103150419.3923421-2-bhupesh.sharma@linaro.org |
---|---|
State | New |
Headers | show |
Series | Add Qualcomm SM6115 / SM4250 EUD dt-bindings & driver support | expand |
On 03/01/2023 16:04, Bhupesh Sharma wrote: > Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. > > On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' > needs to be set first to 'enable' the eud module. > Subject: drop second, redundant "binding". > So, update the dt-bindings to accommodate the third register > property required by the driver on these SoCs. > > Cc: Souradeep Chowdhury <quic_schowdhu@quicinc.com> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > index c98aab209bc5d..1dffe14868735 100644 > --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > @@ -18,12 +18,22 @@ properties: > items: > - enum: > - qcom,sc7280-eud > + - qcom,sm6115-eud > - const: qcom,eud > > reg: > + minItems: 2 > items: > - description: EUD Base Register Region > - description: EUD Mode Manager Register > + - description: TCSR Check Register Is this valid also for sc7280? From commit description looks like not, so you should have allOf:if:then constraining the items per variant. > + > + reg-names: > + minItems: 2 > + items: > + - const: eud-base > + - const: eud-mode-mgr > + - const: tcsr-check-base > > interrupts: > description: EUD interrupt Best regards, Krzysztof
Hi, On Fri, 6 Jan 2023 at 14:43, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 03/01/2023 16:04, Bhupesh Sharma wrote: > > Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. > > > > On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' > > needs to be set first to 'enable' the eud module. > > > > Subject: drop second, redundant "binding". > > > > So, update the dt-bindings to accommodate the third register > > property required by the driver on these SoCs. > > > > Cc: Souradeep Chowdhury <quic_schowdhu@quicinc.com> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > > index c98aab209bc5d..1dffe14868735 100644 > > --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > > @@ -18,12 +18,22 @@ properties: > > items: > > - enum: > > - qcom,sc7280-eud > > + - qcom,sm6115-eud > > - const: qcom,eud > > > > reg: > > + minItems: 2 > > items: > > - description: EUD Base Register Region > > - description: EUD Mode Manager Register > > + - description: TCSR Check Register > > Is this valid also for sc7280? From commit description looks like not, > so you should have allOf:if:then constraining the items per variant. Ok, I will fix and send an updated version. Thanks, Bhupesh > > + > > + reg-names: > > + minItems: 2 > > + items: > > + - const: eud-base > > + - const: eud-mode-mgr > > + - const: tcsr-check-base > > > > interrupts: > > description: EUD interrupt > > Best regards, > Krzysztof >
On Tue, Jan 03, 2023 at 08:34:18PM +0530, Bhupesh Sharma wrote: > Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. > > On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' > needs to be set first to 'enable' the eud module. > > So, update the dt-bindings to accommodate the third register > property required by the driver on these SoCs. > > Cc: Souradeep Chowdhury <quic_schowdhu@quicinc.com> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > index c98aab209bc5d..1dffe14868735 100644 > --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml > @@ -18,12 +18,22 @@ properties: > items: > - enum: > - qcom,sc7280-eud > + - qcom,sm6115-eud > - const: qcom,eud > > reg: > + minItems: 2 > items: > - description: EUD Base Register Region > - description: EUD Mode Manager Register > + - description: TCSR Check Register So this is going to be a 4 byte region in the middle of the &tcsr block? Could we instead make that a reference to &tcsr + offset? Regards, Bjorn > + > + reg-names: > + minItems: 2 > + items: > + - const: eud-base > + - const: eud-mode-mgr > + - const: tcsr-check-base > > interrupts: > description: EUD interrupt > -- > 2.38.1 >
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index c98aab209bc5d..1dffe14868735 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,12 +18,22 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: + minItems: 2 items: - description: EUD Base Register Region - description: EUD Mode Manager Register + - description: TCSR Check Register + + reg-names: + minItems: 2 + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-check-base interrupts: description: EUD interrupt
Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property required by the driver on these SoCs. Cc: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> --- .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)