From patchwork Mon Mar 6 17:08:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lux Aliaga X-Patchwork-Id: 660652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A12BC61DA4 for ; Mon, 6 Mar 2023 17:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbjCFRWP (ORCPT ); Mon, 6 Mar 2023 12:22:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229813AbjCFRWN (ORCPT ); Mon, 6 Mar 2023 12:22:13 -0500 Received: from amity.mint.lgbt (vmi888983.contaboserver.net [149.102.157.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ADF864AA2 for ; Mon, 6 Mar 2023 09:21:40 -0800 (PST) Received: from amity.mint.lgbt (mx.mint.lgbt [127.0.0.1]) by amity.mint.lgbt (Postfix) with ESMTP id 4PVlRR1lSxz1S5KG for ; Mon, 6 Mar 2023 12:09:07 -0500 (EST) Authentication-Results: amity.mint.lgbt (amavisd-new); dkim=pass (2048-bit key) reason="pass (just generated, assumed good)" header.d=mint.lgbt DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mint.lgbt; h= content-transfer-encoding:mime-version:references:in-reply-to :x-mailer:message-id:date:subject:to:from; s=dkim; t=1678122546; x=1678986547; bh=7xRNWZDL/30mtu3WxKxjUXO6ZS/+UYamjJhFWwATyYA=; b= CtzMlXm7534pQoLllMhDj1SOk+SJ58mespiY09wTMLYQq0BEBpznntS31JjbFSUK ccqXx4VJcTRuW/yBzVN/CCn8ZqX8KVOu5yfSd28l3QRNS8GIBXktaiJNOz6c7yK8 Uu1Mz7027WNc+3z5r3SBuLQzQJ3uET22cuo3Z6E7Dw3qu7aJAcHuyAg/z5+RwwTI hyIUWGzTHaGvjg1OI081Q9G5fL7aOgqSlhvt8jlWN0+jwWxS7qMMJeW4K8RT9/JA H/pCnPSqtFQgh/UIDKfm+UWncJCo9qEaO2oNT1vBeudQNF9M68NcT8mUGhG3KZd4 MMiogDy1/R0VzvPt9LEMmQ== X-Virus-Scanned: amavisd-new at amity.mint.lgbt Received: from amity.mint.lgbt ([127.0.0.1]) by amity.mint.lgbt (amity.mint.lgbt [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id lYhEiyPJ4A30 for ; Mon, 6 Mar 2023 12:09:06 -0500 (EST) Received: from dorothy.. (unknown [186.105.8.42]) by amity.mint.lgbt (Postfix) with ESMTPSA id 4PVlRF2xYQz1S5Jr; Mon, 6 Mar 2023 12:08:57 -0500 (EST) From: Lux Aliaga To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com Cc: ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, linux-hardening@vger.kernel.org, phone-devel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org, Lux Aliaga Subject: [PATCH v7 4/6] arm64: dts: qcom: sm6125: Add UFS nodes Date: Mon, 6 Mar 2023 14:08:14 -0300 Message-Id: <20230306170817.3806-5-they@mint.lgbt> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230306170817.3806-1-they@mint.lgbt> References: <20230306170817.3806-1-they@mint.lgbt> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds a UFS host controller node and its corresponding PHY to the sm6125 platform. Signed-off-by: Lux Aliaga --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 62 ++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index df5453fcf2b9..7384d88f44cc 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -511,6 +511,68 @@ sdhc_2: mmc@4784000 { status = "disabled"; }; + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + freq-table-hz = <50000000 240000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <75000000 300000000>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + #reset-cells = <1>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + lanes-per-direction = <1>; + + iommus = <&apps_smmu 0x200 0x0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6125-qmp-ufs-phy"; + reg = <0x04807000 0xdb8>; + + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + gpi_dma0: dma-controller@4a00000 { compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x04a00000 0x60000>;