diff mbox series

[V6,7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM

Message ID 20230307062232.4889-8-quic_kathirav@quicinc.com
State Accepted
Commit 9e4a7652d7028d40b2dd6636d400ca6266d641ef
Headers show
Series Add minimal boot support for IPQ5332 | expand

Commit Message

Kathiravan Thirumoorthy March 7, 2023, 6:22 a.m. UTC 
Document the compatible for IPQ5332 SCM.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V6:
	- No changes

Changes in V5:
	- No changes

Changes in V4:
	- No changes

Changes in V3:
	- No changes

Changes in V2:
	- Added the 'Acked-by' tag

 Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
 1 file changed, 1 insertion(+)

Comments

Konrad Dybcio March 8, 2023, 3:44 p.m. UTC | #1 
On 8.03.2023 16:39, Kathiravan T wrote:
> 
> On 3/8/2023 4:31 PM, Konrad Dybcio wrote:
>>
>> On 7.03.2023 07:22, Kathiravan T wrote:
>>> Document the compatible for IPQ5332 SCM.
>>>
>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>> ---
>> Does this board not have a crypto engine / CE1 clock exposed via
>> RPMCC? It will be enabled by default, but Linux should be aware
>> of it, so that we don't gate it by accident.
> 
> 
> IPQ5332 doesn't have the crypto engine and also it doesn't have RPMCC. Sorry, could you please help to explain how it is related to SCM?
SCM usually requires certain clocks to be up and that often includes
the CE1 clock on fairly recent designs.

Konrad
> 
> Thanks, Kathiravan T.
Kathiravan Thirumoorthy March 9, 2023, 4:47 a.m. UTC | #2 
On 3/8/2023 9:14 PM, Konrad Dybcio wrote:
>
> On 8.03.2023 16:39, Kathiravan T wrote:
>> On 3/8/2023 4:31 PM, Konrad Dybcio wrote:
>>> On 7.03.2023 07:22, Kathiravan T wrote:
>>>> Document the compatible for IPQ5332 SCM.
>>>>
>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>>> ---
>>> Does this board not have a crypto engine / CE1 clock exposed via
>>> RPMCC? It will be enabled by default, but Linux should be aware
>>> of it, so that we don't gate it by accident.
>>
>> IPQ5332 doesn't have the crypto engine and also it doesn't have RPMCC. Sorry, could you please help to explain how it is related to SCM?
> SCM usually requires certain clocks to be up and that often includes
> the CE1 clock on fairly recent designs.


Thanks for the explanation. I don't see such requirements for this SoC.


> Konrad
>> Thanks, Kathiravan T.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index a66e99812b1f..c1adbb83734b 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -24,6 +24,7 @@  properties:
           - qcom,scm-apq8064
           - qcom,scm-apq8084
           - qcom,scm-ipq4019
+          - qcom,scm-ipq5332
           - qcom,scm-ipq6018
           - qcom,scm-ipq806x
           - qcom,scm-ipq8074