From patchwork Fri Mar 24 02:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 666993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C6BCC77B60 for ; Fri, 24 Mar 2023 02:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229522AbjCXCZ5 (ORCPT ); Thu, 23 Mar 2023 22:25:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231388AbjCXCZx (ORCPT ); Thu, 23 Mar 2023 22:25:53 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5E3D2A174 for ; Thu, 23 Mar 2023 19:25:52 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id j11so371373lfg.13 for ; Thu, 23 Mar 2023 19:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679624752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9PaZ61W9t4KfC8rddudNCJ7+Nn2ok2h0HeOnfxFX6Ng=; b=C1d300p6IneOJKse6RlBic9sZOBerrET5woG2W0m8xbjYyaIzjALZL71PphiZL4PQG Pz5f0g9feOVl3wiTfnARP/ID0WLfYYcNjXGA8+J/4aO46RXOkGtMBsfCOzOwWiNBUgnL hcpjDj3NLHqFW8HWz7uFm6nUKWMqVSFmfb0Upp+QEKimj39BQI3oDunSJfX80GDwtkmF a0h0NKxCnV95r0BQ0ML4pbkv1JjbWg89gWP3cjVKhIX8af8gJYzMFYBR67Lhq7JIg2d5 ertGsvkoESrshSLg4jRqAW08C8dwyLaOt0+srxj8k3f43AW0Awi1k0GyiPq5pk78db6D gDqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679624752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9PaZ61W9t4KfC8rddudNCJ7+Nn2ok2h0HeOnfxFX6Ng=; b=zXEv7bc5/MpbKyaD49tgVb5DDzpDz0oHBW0MVzKDwOgHs5sYdOuYRJ7DDCMdSegzBQ YdHW9uoq6+HP8uedi0XnFaL+1z+dytnOPxkWIuwim5lBMhJRc23JY7BErnH+au7vcQZr +7NyKdjNuk4hozsSLx/MqmZooutSIBDucK+/Neh4K4681w9PR4GzrjHa/U+kU3YdriFs +CDEDb2RHovByillzR0k88CfwkGYhUPcrBLT95S/rWMucJLsrU4mtBbGLd7kofOZvQ/C CWnSnniI5KXfZnPL+15dmB67axA/Igvlgn7ePDn3aVaTf7fYxPIcF6qgsnulFi8WTqil akNg== X-Gm-Message-State: AAQBX9efL8YwTCDQNHZnAHek3eV25lJlweM2NrB0BRHx+b4kEQMH1bul y3MHzZHuLFHtX0CaeHpFCp6kdg== X-Google-Smtp-Source: AKy350Z4SrYLCs6LjCqrJSgVxMyUIj5SIP1W61Qe/ahjnM0hsArBQjOkOVBHq0E8klLpmiqdodugYw== X-Received: by 2002:ac2:46dc:0:b0:4dc:4fe2:2aad with SMTP id p28-20020ac246dc000000b004dc4fe22aadmr238731lfo.41.1679624752298; Thu, 23 Mar 2023 19:25:52 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x4-20020a19f604000000b004db3aa3c542sm3162628lfe.47.2023.03.23.19.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 19:25:51 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold Subject: [PATCH 35/41] arm64: dts: qcom: sdm845: switch PCIe QMP PHY to new style of bindings Date: Fri, 24 Mar 2023 05:25:08 +0300 Message-Id: <20230324022514.1800382-36-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230324022514.1800382-1-dmitry.baryshkov@linaro.org> References: <20230324022514.1800382-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 71 ++++++++++++---------------- 1 file changed, 30 insertions(+), 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6eb82c5641cd..9cad1be584da 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1182,8 +1182,8 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <&pcie0_lane>, - <&pcie1_lane>; + <&pcie0_phy>, + <&pcie1_phy>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", @@ -2354,7 +2354,7 @@ pcie0: pci@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; status = "disabled"; @@ -2362,15 +2362,22 @@ pcie0: pci@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sdm845-qmp-pcie-phy"; - reg = <0 0x01c06000 0 0x18c>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c06000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -2379,19 +2386,6 @@ pcie0_phy: phy@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x01c06200 0 0x128>, - <0 0x01c06400 0 0x1fc>, - <0 0x01c06800 0 0x218>, - <0 0x01c06600 0 0x70>; - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; }; pcie1: pci@1c08000 { @@ -2464,7 +2458,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; status = "disabled"; @@ -2472,15 +2466,22 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0a000 { compatible = "qcom,sdm845-qhp-pcie-phy"; - reg = <0 0x01c0a000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0a000 0 0x2000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2489,18 +2490,6 @@ pcie1_phy: phy@1c0a000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c06200 { - reg = <0 0x01c0a800 0 0x800>, - <0 0x01c0a800 0 0x800>, - <0 0x01c0b800 0 0x400>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; mem_noc: interconnect@1380000 {