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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id g6-20020a2e9cc6000000b002af0e9abaf6sm159224ljj.131.2023.05.17.09.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 09:50:15 -0700 (PDT) From: Konrad Dybcio Date: Wed, 17 May 2023 18:50:08 +0200 Subject: [PATCH 1/6] drm/msm/a6xx: Explain CP_PROTECT_CNTL writes in a6xx_set_cp_protect MIME-Version: 1.0 Message-Id: <20230517-topic-a7xx_prep-v1-1-7a964f2e99c2@linaro.org> References: <20230517-topic-a7xx_prep-v1-0-7a964f2e99c2@linaro.org> In-Reply-To: <20230517-topic-a7xx_prep-v1-0-7a964f2e99c2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684342212; l=1118; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=aeaKOCz5rng2fUAGM03IzdiKTh6ymb1woS+RnpEksJ8=; b=kDW/wsHgJ4Xp1eVrDnOZAzxAODW5ws6Zqm/96IDWguKJ8oITdolvZOvBjyGjQEJPILzMHfobA T5r2ncZOohjCdxOLtmFco0HTV27E/+hyiab/rQ4ovzpEwkkpSRj6m5y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We have the necessary information, so explain which bit does what. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9fb214f150dd..deed42675fe2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -771,9 +771,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) } /* - * Enable access protection to privileged registers, fault on an access - * protect violation and select the last span to protect from the start - * address all the way to the end of the register address space + * BIT(0) - Enable access protection to privileged registers + * BIT(1) - Enable fault on an access protect violation + * BIT(3) - Select the last span to protect from the start + * address all the way to the end of the register address space */ gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));