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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id q24-20020a2e9698000000b002ad92dff470sm821384lji.134.2023.05.19.06.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 06:29:23 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 15:29:10 +0200 Subject: [PATCH v2 5/6] drm/msm/a6xx: Improve GMU force shutdown sequence MIME-Version: 1.0 Message-Id: <20230517-topic-a7xx_prep-v2-5-5b9daa2b2cf0@linaro.org> References: <20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@linaro.org> In-Reply-To: <20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , Jonathan Marek , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684502955; l=999; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=tIqOHRwnY5c8M0EJh8c6iF51VO5nfDTSDxvclL4zDow=; b=KYPo2qeuYKLdvjj9oKoR1uGIGtpjAhcYDxd18dm3Lwi5iPiyTSKITY8bEUzM2vOEEa3w8ByAg sTMUWlNlnzwBn7Mt3wFvyNRhmol24Y9mXySPWHFi9n360y5ZUZIDaAF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GMU force shutdown sequence involves some additional register cleanup which was not implemented previously. Do so. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index ea6d671e7c6c..8004b582e45f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -930,6 +930,13 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) /* Make sure there are no outstanding RPMh votes */ a6xx_gmu_rpmh_off(gmu); + /* Clear the WRITEDROPPED fields and put fence into allow mode */ + gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7); + gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); + + /* Make sure the above writes go through */ + wmb(); + /* Halt the gmu cm3 core */ gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);