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[83.9.3.193]) by smtp.gmail.com with ESMTPSA id u26-20020a056512041a00b004f764716afdsm314395lfk.257.2023.06.20.04.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 04:10:42 -0700 (PDT) From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:37 +0200 Subject: [PATCH v4 2/6] drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL MIME-Version: 1.0 Message-Id: <20230517-topic-a7xx_prep-v4-2-b16f273a91d4@linaro.org> References: <20230517-topic-a7xx_prep-v4-0-b16f273a91d4@linaro.org> In-Reply-To: <20230517-topic-a7xx_prep-v4-0-b16f273a91d4@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , Jonathan Marek , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687259438; l=1047; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=M+YceCSQbhF8BD7s1Uycd683ewMShr4OUbGYlX/cKSo=; b=Xf8hG5l+ir4khCTVmKbLCZnf4B5dK4hruBv6ZR33xJp5az1Bv32pwYt6r/ytPDp6yrEHct+hI KhUiDXIjdShDMyyvJymRLqYM0VWGJt1rbRunrDvooo1y6+oYXaH6RDa X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We have the necessary information, so explain which bit does what. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b3ada1e7b598..cd0c9bccdc19 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -930,7 +930,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) * protect violation and select the last span to protect from the start * address all the way to the end of the register address space */ - gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); + gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, + A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | + A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | + A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); for (i = 0; i < count - 1; i++) gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);