From patchwork Wed May 17 00:07:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 683053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0698C7EE24 for ; Wed, 17 May 2023 00:07:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231165AbjEQAHr (ORCPT ); Tue, 16 May 2023 20:07:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229631AbjEQAHq (ORCPT ); Tue, 16 May 2023 20:07:46 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E48C012F for ; Tue, 16 May 2023 17:07:44 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2ac81d2bfbcso335511fa.3 for ; Tue, 16 May 2023 17:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684282063; x=1686874063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FBAkVdbh6cPTMjC6o2ySkEa6jNcEcZVNqgzdILUk71Q=; b=Lkvr42oyvm36IDn9i4bS0+QJGivQpD+Dq7vougv6yb4iJdbPYLQ7Zfa7qyM/OwaxDi 55FMofaBEJsbpvlGQReBUEdnt1MufwfVw4y4QLj0T4z7ovA8EM8Bs59AZI7pgNImsC0i yluRFP/fQcBUVrF8oxunGrzCbVNORws7R7J8UJaIAEbSZtxudVlPcSbau0vZZdb7VKih ramC72pFphlBI2VVy+N1eY0sQsUyhvWQSywO1PihITdSJ2yYNmZlHEbTNyzT/F66gE4k HVawDCO9fu6swWhGbaVj5YTjCF+8KAwhKorwMdu1uftinUzcsVA/jbMBzfTAylhEeZwC Gh3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684282063; x=1686874063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FBAkVdbh6cPTMjC6o2ySkEa6jNcEcZVNqgzdILUk71Q=; b=K64XzyWrmFcT9eU/YJtQxTpwbDxAnOKgPgDR+FSzaYHdObI3rdTexe7hWxiIHyDXlC lORmKqqkOm9k1BL/T46WCs2QdbNAnfGXkvhtBXI+nhJ4Fj0ODVpQU6TAFD+nk1oKC0et IvlrMf5QZOumP3wwMmtcIz9MB+qWw9z6itB0RTuriOw/TYTZ4RBhFRvdhfzgwST1dM0Z OE6BpgOM8/OThmco5UBC6TfM0KS162/lzwZj7KJjnNqsVpX/ozIT8iUwwb50Kgdx8esR qHal6oxba6QdEtVWFNXNlZKlV1tJedYh7BdICm+LGwZb0fGXH9lyFFZScNTZcskF6p9w RrXQ== X-Gm-Message-State: AC+VfDzp4Jecu3w4hBU8DkKMlCjo6T1KFlAI5aXnN5U5YeT0KaVFMxKs P6EBRA7CxmQdDWp6rYPYbj3oMw== X-Google-Smtp-Source: ACHHUZ4/f+bfJRSGJyE9FP9M19yDbYcNiVGa/8NNgQ2BXehGueMhmETXKFy8MUTx3NHwlrZi+yREDQ== X-Received: by 2002:a2e:80cd:0:b0:2ad:8c4a:ef7e with SMTP id r13-20020a2e80cd000000b002ad8c4aef7emr10113992ljg.43.1684282063168; Tue, 16 May 2023 17:07:43 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id y22-20020a2e9d56000000b002ac71095b61sm4214858ljj.64.2023.05.16.17.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 17:07:42 -0700 (PDT) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Suraj Kandpal , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Jani Nikula Subject: [PATCH v6 1/8] drm/i915/dsc: change DSC param tables to follow the DSC model Date: Wed, 17 May 2023 03:07:33 +0300 Message-Id: <20230517000740.2102599-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230517000740.2102599-1-dmitry.baryshkov@linaro.org> References: <20230517000740.2102599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After cross-checking DSC models (20150914, 20161212, 20210623) change values in rc_parameters tables to follow config files present inside the DSC model. Handle two places, where i915 tables diverged from the model, by patching the rc values in the code. Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because the table in the VESA DSC 1.1 sets it to 4. Reviewed-by: Jani Nikula Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/i915/display/intel_vdsc.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 8e787c13d26d..7003ae9f683a 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -87,7 +87,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { } }, /* 6BPP/14BPC */ - { 768, 15, 6144, 15, 25, 23, 27, { + { 768, 15, 6144, 15, 25, 23, 23, { { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, @@ -116,6 +116,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { }, /* 8BPP/10BPC */ { 512, 12, 6144, 7, 16, 15, 15, { + /* + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however + * VESA DSC 1.1 Table E-5 sets it to 4. + */ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, @@ -133,7 +137,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { }, /* 8BPP/14BPC */ { 512, 12, 6144, 15, 24, 23, 23, { - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, @@ -598,6 +602,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) DSC_RANGE_BPG_OFFSET_MASK; } + if (DISPLAY_VER(dev_priv) < 13) { + /* + * FIXME: verify that the hardware actually needs these + * modifications rather than them being simple typos. + */ + if (compressed_bpp == 6 && + vdsc_cfg->bits_per_component == 8) + vdsc_cfg->rc_quant_incr_limit1 = 23; + + if (compressed_bpp == 8 && + vdsc_cfg->bits_per_component == 14) + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0; + } + /* * BitsPerComponent value determines mux_word_size: * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to